單片機(jī)的功能和結(jié)構(gòu)外文翻譯@中英文翻譯@外文文獻(xiàn)翻譯

Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer MCS-51 is a name of a piece of one-chip computer series which Intel Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers . An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositting not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, such as 8031 , 8032, 80C ,etc. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip computer and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, storing device 2 temporarily, 8s accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses in the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded. There are ROM (procedure memory , can only read ) and RAM in 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and general microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM can arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of location , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. 8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off； P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouths, its output grade draws the resistance supremly. When using it as the mouth in common use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should write 1 to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistance value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate , can draw the pin to the high level fast ； When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ordinary times, can is it draw electric current load to offer outwards, draw the resistance on neednt answer and thenning. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end. Relatively about 20,000 ohms because of the load resistance in scene and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1. P3 mouth one multi-functional port, mouth getting many than P1 it have and 3 door and 4 buffer. Two part these, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, and door 3 function one switch in fact, it determines to be to output data of latch to output second signal of function. Act as W =At 1 oclock, output Q end signal； Act as Q =At 1 oclock, can output W line signal . At the time of programming, it is that the first function is still the second function but neednt have software that set up P3 mouth in advance . It hardware not inside is the automatic to have two function outputted when CPU carries on SFR and seeks the location (the location or the byte ) to visit to P3 mouth /at not lasting lining, there are inside hardware latch Qs =1.The operation principle of P3 mouth is similar to P1 mouth. Output grade , P3 of mouth , P1 of P1 , connect with inside have load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of output electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1P3 Being restored to the throne is the operation of initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate there arent mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 shake cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne the signal: Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitts trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop ones head and monitor the pin with the oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change. 51 系列單片機(jī)的功能和結(jié)構(gòu) 結(jié)構(gòu)和功 能的監(jiān)控監(jiān) -51 系列之一 -計(jì)算機(jī)芯片監(jiān)控監(jiān) -51 名是一幅一個(gè)電腦晶片 ,英特爾公司生產(chǎn)系列 . 這家公司推出 8 級(jí)一個(gè)計(jì)算機(jī)芯片監(jiān)控監(jiān) -51 系列之后 ,于 1980 年 8引入一個(gè)計(jì)算機(jī)芯片監(jiān)控監(jiān) ,于 1976 年 48系列 .。它屬于這一類型很多行一個(gè)芯片的電腦芯片都如 8051、 8031、 8751、 80c51bh,80c31bh等 ,其基本組成、性能和基本教學(xué)制度 ,都是一樣的 . 8051 每日代表 -51 系列之一-電腦晶片 有一個(gè)芯片的計(jì)算機(jī)系統(tǒng)是由以下幾個(gè)方面 : (1)18 微處理器(CPU). (2)在切片數(shù)據(jù)存儲(chǔ)羊 (128B/256B),使用可以不讀書不數(shù)據(jù)寫如因經(jīng)營(yíng)不中 ,最后結(jié)果要和數(shù)據(jù)顯示等 . (3)存儲(chǔ)器存儲(chǔ)程序 /可擦寫可編程只讀存儲(chǔ)器(4KB/8KB),用于保存程序和數(shù)據(jù) ,初步形成片 . 但并不存儲(chǔ)器 /可擦寫可編程只讀存儲(chǔ)器在一些人的電腦芯片 ,如 8031、 8032、 80c 等 . （ 4)經(jīng)營(yíng)的 84并肩一 /四 OP0P3 接口 ,每口可以用作介紹 ,也可以用作輸出 . (5)兩個(gè)定時(shí) /柜臺(tái) ,每個(gè)計(jì)時(shí)器 /柜臺(tái)可設(shè)立和計(jì)算的方法 ,用來計(jì)算的外部事件 ,可以建立成一個(gè)時(shí)間的方式也可以和根據(jù)計(jì)算結(jié)果或時(shí)間實(shí)現(xiàn)控制的計(jì)算 (六 )五切斷切斷源頭上控 制系統(tǒng) . (七 )各一序 I/O 口 UART(異步接收世界 /發(fā)送 (UART),它是實(shí)現(xiàn)一個(gè)計(jì)算機(jī)芯片和一個(gè)計(jì)算機(jī)芯片和通訊系列電腦上使用 . (8)強(qiáng)、時(shí)鐘振蕩器電路生產(chǎn)、水晶石英細(xì)調(diào)需要外部電容 . 為使振動(dòng)頻率目前最 . 每上述地區(qū)內(nèi)的數(shù)據(jù)是通過加入單片機(jī) . 其中 ,CPU 的核心是一個(gè)電腦芯片 ,它是計(jì)算機(jī)和指揮控制中心等部分組成 ,運(yùn)算器和控制等 . 運(yùn)算器的可攜帶 8 人計(jì)算 a 經(jīng)營(yíng)單位的經(jīng)營(yíng)邏輯 ,其中 ,1temporarilies 存儲(chǔ)裝置 8、暫時(shí)貯存器 2、 8的行政協(xié)調(diào)會(huì)累積裝置、 B、注冊(cè)登記程序國(guó)有 PSW 等 . 累積計(jì) 200人 ,行政協(xié)調(diào)委員會(huì)結(jié)束對(duì)進(jìn)入檢查 . 暫時(shí)運(yùn)作往往是來自一店經(jīng)營(yíng)者 ,這是經(jīng)營(yíng)下去 ,使計(jì)暫時(shí)經(jīng)營(yíng)成果和行政協(xié)調(diào)會(huì) . 此外 ,行政協(xié)調(diào)會(huì)經(jīng)常被視為轉(zhuǎn)運(yùn)站 ,在 8051 年的數(shù)據(jù)傳輸 . 一般微處理器一樣 ,是繁忙登記 . 幫助大家 ,表示了贊同的命令 . 控制程序包括柜臺(tái)命令詳解 ,振蕩器電路和時(shí)間等 . 程序相當(dāng)于 16. 這是一個(gè)字節(jié)地址位的程序 ,其實(shí) ,內(nèi)容是未來 IA 將進(jìn)行 PC. 修改的內(nèi)容 ,它可以改變方向 ,進(jìn)行程序 . 在 8051 電路動(dòng)搖一個(gè)電腦芯片、石英晶體外 ,只需要相當(dāng)頻繁調(diào)整電容 ,其范圍是 12mhz 的頻率1.2mhz. 這 一脈沖信號(hào) ,作為 8051 年工作的基本節(jié)拍 ,即單位時(shí)間內(nèi)的最低 . 8051 年是計(jì)算機(jī)一樣 ,在和諧的工作基本控制打 ,就像打了一個(gè)樂團(tuán) ,按照發(fā)揮 ,指揮 . 有存儲(chǔ)器 (程序存儲(chǔ)器 ,只能讀 ),8051 年在羊片 (存儲(chǔ)數(shù)據(jù) ,是可以寫出 )二讀 ,他們每個(gè)獨(dú)立存儲(chǔ)空間處理 ,處理方式是一樣的 ,一般的電腦記憶 . 8051 年和 8751 年撥款程序存儲(chǔ)程序存貯器 4kb,從 0000h 地址 ,用于保存程序和方式不變 . 數(shù)據(jù) 8051-87518031128b記憶存儲(chǔ)數(shù)據(jù) ,00fh假地址 ,用于存放操作結(jié)果中 ,暫時(shí)儲(chǔ)存數(shù)據(jù)和資料等無人。在這種羊 128b,有 32 個(gè)單位字節(jié)可以出任就業(yè)登記 ,這是與一般不同的微處理器、 8051 切片和就業(yè)登記成立一個(gè)級(jí)別相同的地點(diǎn)安排 . 這是很不相同的記憶監(jiān)控監(jiān) -51 系列之一 -計(jì)算機(jī)芯片 ,除了一般電腦的方式處置 . 一般電腦先向空間、存儲(chǔ)器和 RAM,可安排在不同的空間范圍內(nèi)解決這一意愿 ,即存儲(chǔ)器的地址和 RAM,地址分配不同的空間形成 . 同時(shí)來訪的記憶 ,相應(yīng)的存儲(chǔ)器 ,只有一個(gè)地址 ,可以存儲(chǔ) ,也可以撞擊 ,并以同樣的訪問 . 這種記憶結(jié)構(gòu)稱為普林斯頓結(jié)構(gòu) . 8051 記憶分為程序存儲(chǔ)空間和數(shù)據(jù)存儲(chǔ)空間的物理結(jié)構(gòu) ,有四個(gè)存儲(chǔ)空間 :我們的程 序儲(chǔ)存在一個(gè)數(shù)據(jù)存儲(chǔ)空間之外的數(shù)據(jù)存儲(chǔ)和一個(gè)程序存儲(chǔ)空間、外一、結(jié)構(gòu)形式的這種程序裝置和數(shù)據(jù)存儲(chǔ)與形式的數(shù)據(jù)存儲(chǔ) ,稱為哈佛結(jié)構(gòu) . 但用用戶的角度 ,討論 8051 年的記憶空間分為三類 :(1)在時(shí)代安排 Ffffh 座 ,0000h 地點(diǎn)、從容外片 (地址用十六 ). (二 )處理數(shù)據(jù)存儲(chǔ)空間之外 64kb 之一 ,被安排從地址 0000hFfffh64kb(地址 16),地點(diǎn)太 . 三 )處理數(shù)據(jù)存儲(chǔ)空間 256b(地址 8 使用 ). 上述三個(gè)存儲(chǔ)空間地址重疊 ,鑒別設(shè)計(jì) ,象征不同的數(shù)據(jù)傳輸?shù)恼Z言系統(tǒng) 8051:CPU訪問片 ,以存儲(chǔ)器 ,阻止訪問命令 Ra用途外用一張旅游片。 8051 年 1-48 芯片計(jì)算機(jī)與我走 /澳港 ,要求 P0、 P1、 P2 和 P3. 每個(gè)港口 8準(zhǔn)確雙向口 ,共占 32 別針 . 每一個(gè)我 /O 線可作為引進(jìn)和輸出獨(dú)立 . 每個(gè)港口有門閂 (即登記特殊功能 )、駕駛?cè)恕⒊隹趯?shí)行緩沖 . 可當(dāng)門閂使 outputting 數(shù)據(jù) ,數(shù)據(jù)可以緩沖時(shí)推出 ,但這些四個(gè)功能自我同一 . 在擴(kuò)大對(duì)外開放具有時(shí)代記憶系統(tǒng) ,這四個(gè)港口可準(zhǔn)確雙向口一 /O 共同使用。在擴(kuò)大對(duì)外開放具有時(shí)代記憶系統(tǒng) ,高 8P2 口地址見客 . P0 口是一個(gè)雙向車采用 8 送數(shù)據(jù)低 地址 /出口Timesharing 在 8051年的巡回一個(gè)計(jì)算機(jī)芯片和四個(gè)一 /O港口很巧妙的設(shè)計(jì) . 熟悉我 /港澳邏輯電路 ,不僅有利于正確、合理地使用港口、激勵(lì)周邊邏輯電路設(shè)計(jì)的一個(gè)計(jì)算機(jī)芯片有所提高 . 負(fù)載能力和接口港口有一定的要求 ,因?yàn)楫a(chǎn)量等 ,