電子科技大學數(shù)字邏輯設(shè)計及應(yīng)用lec17chap 7

1、1digital logic design and applicatonlecture #17latches and flip-flopsuestc, spring 2013digital logic design and application2再談串行輸入加法器的實現(xiàn)再談串行輸入加法器的實現(xiàn)q dq cxycisici+1xiyiciscoclk 暫存暫存 x yci cosci+1sixi yici時鐘控制時鐘控制 電平有效還是邊沿有效？電平有效還是邊沿有效？串行輸入、串行輸出串行輸入、串行輸出注意：注意：時鐘同步時鐘同步iterative vs. sequentialdigital l

2、ogic design and application3iterative versus sequential circuitsc0c4x0 y0x1 y1x2 y2x3 y3s0s1s2s3digital logic design and application47.2 latches and flip-flopslatcheschange its outputs at any time (enable input is asserted).flip-flopschange its outputs only when the clock changesclkpositive-edgerisi

3、ng-edgenegative-dgefalling-edgelevel triggerededge-triggered, etdigital logic design and application57.2.5 edge-triggered d flip-flopsd qc qd qc qqqldclkmaster slaveqm when clk=0, when clk=1, qm follows d; q is unchanging.qm is unchanging, q = qm until the next rising clk edge1. master/slave, positi

4、ve-edge-triggeredq changes only when clk rises from 0 to 1digital logic design and application6timing diagram for master-slave d f/fdclkqqmd qc qd qc qqqldclkqmq =d( )digital logic design and application7dclkqd q clk qlogic symboledge-triggered digital logic design and application8dclkqdclkqd latch

5、d latch d flip-flop d flip-flop edge-triggered when clk is asserted對信號擾動不敏感對信號擾動不敏感受信號擾動影響受信號擾動影響digital logic design and application9d flip-flop timing parameterspropagation delay ( from clk )tplh(cq) tphl(cq) tsetup建立時間建立時間 thold 保持時間保持時間 setup time ( d before clk）hold time ( d after clk)d clkq在時鐘

6、上升邊沿附近有一個時間窗口，在此窗口時間內(nèi)，數(shù)據(jù)輸入在時鐘上升邊沿附近有一個時間窗口，在此窗口時間內(nèi)，數(shù)據(jù)輸入d d不能不能改變，否則電路進入亞穩(wěn)態(tài)。改變，否則電路進入亞穩(wěn)態(tài)。從輸入信號從輸入信號d d到來時刻至信號到來時刻至信號d d達到穩(wěn)定所持續(xù)的時間。達到穩(wěn)定所持續(xù)的時間。從輸入信號從輸入信號d d達到穩(wěn)定至信號達到穩(wěn)定至信號d d被鎖存器接受所持續(xù)的時間。被鎖存器接受所持續(xù)的時間。digital logic design and application102. negative-edge-trigged d flip-flopd qc qd qc qqqndclkd q clk qd

7、qc qd qc qqqldclkpositive-edge-triggereddigital logic design and application3. d flip-flop with preset and clear同步同步(synchronous)是指與是指與時鐘同步時鐘同步，即時鐘，即時鐘觸發(fā)條件滿足時檢測清零觸發(fā)條件滿足時檢測清零(置位置位)信號是否有信號是否有效，有效則在下一個時間周期的觸發(fā)條件下效，有效則在下一個時間周期的觸發(fā)條件下，執(zhí)行清零，執(zhí)行清零(置位置位)；異步異步(asynchronous)是清零是清零(置位置位)信號有效時信號有效時，無視觸發(fā)脈沖，立即清零，無視觸

8、發(fā)脈沖，立即清零(置位置位)。11digital logic design and application123. d flip-flop with preset and clearclkqqldpr_lclr_lprd q clk qclr asynchronous inputs behavior like the set and reset inputs on s-r latch. 1001111101100digital logic design and application13timing diagram for d flip-flop with preset and clearcl

9、kpr_lclr_lqldigital logic design and application3. d flip-flop with preset and clearsynchronous inputs: pr(preset) and clr(clear depend on the clk14d q clk q dinresetclkr有效，有效，q=0r無效，無效，q=din dinreset_ldigital logic design and application154. commercial ttl d flip-flops (74ls74)p535figure 7-20 pr_lc

10、lr_lclkdqqn維持阻塞結(jié)構(gòu)維持阻塞結(jié)構(gòu)smaller and fasterdigital logic design and application165. cmos edge-triggered d circuituses transmission gates in feedback loopsqdclkdclktwo feedback loops (master and slave latches)master slavedigital logic design and application177.2.6 d flip-flop with enable2-inputmultiple

11、xerd q clk qdenclkqqlif en is asserted, the external d input is selected;if en is negated, the current output is used. d qen clk qlogic symbol digital logic design and application187.2.7 scan flip-flopd q clk qdteclkqqltite:test enableti:test inputte=0, d is selected te=1, ti is selectedd teti clk q

12、qdigital logic design and application19toticlktewhen te is negated, q = dwhen te is asserted, q = titoticlktedigital logic design and application207.2.8 master/slave s-r flip-flops qcr qcsrs qcr qqqnqmmasterslavedigital logic design and application21master/slave s-r flip-flop timing diagram暫時忽略延遲時間等

13、動態(tài)特性暫時忽略延遲時間等動態(tài)特性 c unpredictableunpredictabledigital logic design and application22c edge-triggered?unpredictableunpredictablethe s-r flip-flop changes its outputs only at the falling edge of c.but it is not truly edge triggered.pulse-triggered flip-flopsdigital logic design and application237.2.8

14、master/slave s-r flip-flopscrqqd qc qd qc qqqndclks qcr qcsrqqns qcr qpostponed-output indicatord q clk qdynamic input indicator edge triggereddigital logic design and application247.2.9 master/slave j-k flip-flop消除主從消除主從s-rs-r觸發(fā)器存在的約束條件觸發(fā)器存在的約束條件利用反饋消除主從利用反饋消除主從s-rs-r觸發(fā)器存在的約束條件觸發(fā)器存在的約束條件 q* = s + r

15、 qsr = 0 (constraints)s-r ffs qcr qcsrqqns qcr qs = jqr = kqmeet sr=0jkcj-k ff characteristic equationq* = jq + (kq)q(k+q)qkq j k q 0 0 0 11 01 1 hold resetset togglefunction table digital logic design and application257.2.10 edge-triggered j-k flip-flopj-k ff: q* = jq + kqd ff: q* = ddigital logic

16、design and application267.2.11 t flip-flopa t flip-flop changes state on every tick of the clock.qqttoggleen qt qt ff with enabletqdigital logic design and application27design a t flip-flopusing a d flip-flopd ff: q* = dt ff: q* = q d = qusing a j-k flip-flopjk: q* = jq + kq t: q* = q j = k = 1tqqnd

17、 q clk qtqqnj qclk k q1digital logic design and application28t flip-flop with enablet：q* = enq + enq01en q qq* function table jk：q* = jq + kqd：q* = ddigital logic design and application297.2.11 t flip-flop 特征方程：特征方程：q* = q qqt有使能端的有使能端的t觸發(fā)器：觸發(fā)器： q* = enq + enq en qt q說明：說明： 傳統(tǒng)中文教材中認為：傳統(tǒng)中文教材中認為： t 觸發(fā)

18、器的特征方程觸發(fā)器的特征方程 q* = tq + tq t=1時翻轉(zhuǎn)；時翻轉(zhuǎn)；t=0時維持時維持 digital logic design and application30關(guān)于電路結(jié)構(gòu)和邏輯功能關(guān)于電路結(jié)構(gòu)和邏輯功能同一功能的觸發(fā)器可用不同電路結(jié)構(gòu)實現(xiàn)同一功能的觸發(fā)器可用不同電路結(jié)構(gòu)實現(xiàn) 主從結(jié)構(gòu)的主從結(jié)構(gòu)的d觸發(fā)器、維持阻塞結(jié)構(gòu)的觸發(fā)器、維持阻塞結(jié)構(gòu)的d觸發(fā)器觸發(fā)器同類電路結(jié)構(gòu)可做成不同功能的觸發(fā)器同類電路結(jié)構(gòu)可做成不同功能的觸發(fā)器 維持阻塞結(jié)構(gòu)的：維持阻塞結(jié)構(gòu)的：d觸發(fā)器、觸發(fā)器、j-k觸發(fā)器觸發(fā)器電路構(gòu)成的不同形式電路構(gòu)成的不同形式 下一狀態(tài)下一狀態(tài)q* 與與現(xiàn)態(tài)現(xiàn)態(tài)q及輸入之間及輸入之間在穩(wěn)態(tài)下的邏輯關(guān)系在穩(wěn)態(tài)下的邏輯關(guān)系digital lo