DE2-115實(shí)驗(yàn)板引腳配置信息

1、精選優(yōu)質(zhì)文檔-傾情為你奉上DE2-115實(shí)驗(yàn)板引腳配置信息DE2-115開發(fā)板：目標(biāo)芯片Cyclone IV E EP4CE115F29C7；存儲(chǔ)器：64MB x2 SDRAM、2MB SRAM、8MB Flash；通信端口：10/100/1000以太網(wǎng)口 x2、USB 2.0時(shí)鐘：50MHz x3 振蕩器、SMA in/out Altera 配置芯片 EPCS64表 1 撥動(dòng)開關(guān)引腳配置 Signal NameFPGA Pin No.DescriptionI/O StandardSW0PIN_AB28Slide Switch0Depending on JP7SW1PIN_AC28Slide

2、Switch1Depending on JP7SW2PIN_AC27Slide Switch2Depending on JP7SW3PIN_AD27Slide Switch3Depending on JP7SW4PIN_AB27Slide Switch4Depending on JP7SW5PIN_AC26Slide Switch5Depending on JP7SW6PIN_AD26Slide Switch6Depending on JP7SW7PIN_AB26Slide Switch7Depending on JP7SW8PIN_AC25Slide Switch8Depending on

3、JP7SW9PIN_AB25Slide Switch9Depending on JP7SW10PIN_AC24Slide Switch10Depending on JP7SW11PIN_AB24Slide Switch11Depending on JP7SW12PIN_AB23Slide Switch12Depending on JP7SW13PIN_AA24Slide Switch13Depending on JP7SW14PIN_AA23Slide Switch14Depending on JP7SW15PIN_AA22Slide Switch15Depending on JP7SW16P

4、IN_Y24Slide Switch16Depending on JP7SW17PIN_Y23Slide Switch17Depending on JP7表 2 按鈕開關(guān)引腳配置 Signal NameFPGA Pin No.DescriptionI/O StandardKEY0PIN_M23Push-button0Depending on JP7KEY1PIN_M21Push-button1Depending on JP7KEY2PIN_N21Push-button2Depending on JP7KEY3PIN_R24Push-button3Depending on JP7表 3 LED

5、引腳配置 Signal NameFPGA Pin No.DescriptionI/OStandardLEDR0PIN_G19LED Red02.5VLEDR1PIN_F19LED Red12.5VLEDR2PIN_E19LED Red22.5VLEDR3PIN_F21LED Red32.5VLEDR4PIN_F18LED Red42.5VLEDR5PIN_E18LED Red52.5VLEDR6PIN_J19LED Red62.5VLEDR7PIN_H19LED Red72.5VLEDR8PIN_J17LED Red82.5VLEDR9PIN_G17LED Red92.5VLEDR10PIN_

6、J15LED Red102.5VLEDR11PIN_H16LED Red112.5VLEDR12PIN_J16LED Red122.5VLEDR13PIN_H17LED Red132.5VLEDR14PIN_F15LED Red142.5VLEDR15PIN_G15LED Red152.5VLEDR16PIN_G16LED Red162.5VLEDR17PIN_H15LED Red172.5VLEDG0PIN_E21LED Green02.5VLEDG1PIN_E22LED Green12.5VLEDG2PIN_E25LED Green22.5VLEDG3PIN_E24LED Green32.

7、5VLEDG4PIN_H21LED Green42.5VLEDG5PIN_G20LED Green52.5VLEDG6PIN_G22LED Green62.5VLEDG7PIN_G21LED Green72.5VLEDG8PIN_F17LED Green82.5V表 4 七段數(shù)碼管引腳配置 Signal NameFPGA Pin No.DescriptionI/O StandardHEX00PIN_G18Seven Segment Digit 002.5VHEX01PIN_F22Seven Segment Digit 012.5VHEX02PIN_E17Seven Segment Digit

8、022.5VHEX03PIN_L26Seven Segment Digit 03Depending on JP7HEX04PIN_L25Seven Segment Digit 04Depending on JP7HEX05PIN_J22Seven Segment Digit 05Depending on JP7HEX06PIN_H22Seven Segment Digit 06Depending on JP7HEX10PIN_M24Seven Segment Digit 10Depending on JP7HEX11PIN_Y22Seven Segment Digit 11Depending

9、on JP7HEX12PIN_W21Seven Segment Digit 12Depending on JP7HEX13PIN_W22Seven Segment Digit 13Depending on JP7HEX14PIN_W25Seven Segment Digit 14Depending on JP7HEX15PIN_U23Seven Segment Digit 15Depending on JP7HEX16PIN_U24Seven Segment Digit 16Depending on JP7HEX20PIN_AA25Seven Segment Digit 20Depending

10、 on JP7HEX21PIN_AA26Seven Segment Digit 21Depending on JP7HEX22PIN_Y25Seven Segment Digit 22Depending on JP7HEX23PIN_W26Seven Segment Digit 23Depending on JP7HEX24PIN_Y26Seven Segment Digit 24Depending on JP7HEX25PIN_W27Seven Segment Digit 25Depending on JP7HEX26PIN_W28Seven Segment Digit 26Dependin

11、g on JP7HEX30PIN_V21Seven Segment Digit 30Depending on JP7HEX31PIN_U21Seven Segment Digit 31Depending on JP7HEX32PIN_AB20Seven Segment Digit 32Depending on JP6HEX33PIN_AA21Seven Segment Digit 33Depending on JP6HEX34PIN_AD24Seven Segment Digit 34Depending on JP6HEX35PIN_AF23Seven Segment Digit 35Depe

12、nding on JP6HEX36PIN_Y19Seven Segment Digit 36Depending on JP6HEX40PIN_AB19Seven Segment Digit 40Depending on JP6HEX41PIN_AA19Seven Segment Digit 41Depending on JP6HEX42PIN_AG21Seven Segment Digit 42Depending on JP6HEX43PIN_AH21Seven Segment Digit 43Depending on JP6HEX44PIN_AE19Seven Segment Digit 4

13、4Depending on JP6HEX45PIN_AF19Seven Segment Digit 45Depending on JP6HEX46PIN_AE18Seven Segment Digit 46Depending on JP6HEX50PIN_AD18Seven Segment Digit 50Depending on JP6HEX51PIN_AC18Seven Segment Digit 51Depending on JP6HEX52PIN_AB18Seven Segment Digit 52Depending on JP6HEX53PIN_AH19Seven Segment D

14、igit 53Depending on JP6HEX54PIN_AG19Seven Segment Digit 54Depending on JP6HEX55PIN_AF18Seven Segment Digit 55Depending on JP6HEX56PIN_AH18Seven Segment Digit 56Depending on JP6HEX60PIN_AA17Seven Segment Digit 60Depending on JP6HEX61PIN_AB16Seven Segment Digit 61Depending on JP6HEX62PIN_AA16Seven Seg

15、ment Digit 62Depending on JP6HEX63PIN_AB17Seven Segment Digit 63Depending on JP6HEX64PIN_AB15Seven Segment Digit 64Depending on JP6HEX65PIN_AA15Seven Segment Digit 65Depending on JP6HEX66PIN_AC17Seven Segment Digit 66Depending on JP6HEX70PIN_AD17Seven Segment Digit 70Depending on JP6HEX71PIN_AE17Sev

16、en Segment Digit 71Depending on JP6HEX72PIN_AG17Seven Segment Digit 72Depending on JP6HEX73PIN_AH17Seven Segment Digit 73Depending on JP6HEX74PIN_AF17Seven Segment Digit 74Depending on JP6HEX75PIN_AG18Seven Segment Digit 75Depending on JP6HEX76PIN_AA14Seven Segment Digit 763.3V表 5 時(shí)鐘信號(hào)引腳配置信息 Signal NameFPGA Pin No.Description