四位超前進(jìn)位加法器原理

1、精選優(yōu)質(zhì)文檔-傾情為你奉上超前進(jìn)位加法器原理74283為4位超前進(jìn)位加法器，不同于普通串行進(jìn)位加法器由低到高逐級進(jìn)位，超前進(jìn)位加法器所有位數(shù)的進(jìn)位大多數(shù)情況下同時產(chǎn)生，運(yùn)算速度快，電路結(jié)構(gòu)復(fù)雜。其管腳如圖1所示：圖1 74283管腳圖其真值表如下所示：表1 4位超前進(jìn)位加法器真值表由全加器的真值表可得Si和Ci的邏輯表達(dá)式： 定義兩個中間變量Gi和Pi： 當(dāng)AiBi1時，Gi1，由Ci的表達(dá)式可得Ci1，即產(chǎn)生進(jìn)位，所以Gi稱為產(chǎn)生量變 。若Pi1，則Ai·Bi0，CiCi-1，即Pi1時，低位的進(jìn)位能傳送到高位的進(jìn)位輸出端，故Pi稱為傳輸變量，這兩個變量都與進(jìn)位信號無關(guān)。將Gi和P

2、i代入Si和Ci得： 進(jìn)而可得各位進(jìn)位信號的邏輯表達(dá)如下： 根據(jù)邏輯表達(dá)式做出電路圖如下： 邏輯功能圖中有2輸入異或門，2輸入與門，3輸入與門，4輸入與門，2輸入或門，3輸入或門，4輸入或門，其轉(zhuǎn)化成CMOS晶體管圖如下：電路網(wǎng)表如下：*xor 2.subckt xor2 a b c d fmxorpa 1 a vdd vdd pmos l=2 w=8mxorpb f d 1 vdd pmos l=2 w=8mxorpc 2 b vdd vdd pmos l=2 w=8mxorpd f c 2 vdd pmos l=2 w=8mxorna f a 3 0 nmos l=2 w=4mxornb

3、3 b 0 0 nmos l=2 w=4mxornc f c 4 0 nmos l=2 w=4mxornd 4 d 0 0 nmos l=2 w=4.ends xor2 *and2.subckt and2 a b f mandpa f a vdd vdd pmos l=2 w=4mandpb f b vdd vdd pmos l=2 w=4mandna f a 1 0 nmos l=2 w=4mandnb 1 b 0 0 nmos l=2 w=4.ends and2*and3.subckt and3 a b c f mandpa f a vdd vdd pmos l=2 w=4mandpb f

4、 b vdd vdd pmos l=2 w=4mandpc f c vdd vdd pmos l=2 w=4mandna f a 1 0 nmos l=2 w=6mandnb 1 b 2 0 nmos l=2 w=6mandnc 2 c 0 0 nmos l=2 w=6.ends and3*and4.subckt and4 a b c d fmandpa f a vdd vdd pmos l=2 w=4mandpb f b vdd vdd pmos l=2 w=4mandpc f c vdd vdd pmos l=2 w=4mandpd f d vdd vdd pmos l=2 w=4mand

5、na f a 1 0 nmos l=2 w=8mandnb 1 b 2 0 nmos l=2 w=8mandnc 2 c 3 0 nmos l=2 w=8mandnd 3 d 0 0 nmos l=2 w=8.ends and4*or2.subckt or2 a b fmorpa 1 a vdd vdd pmos l=2 w=8morpb f b 1 vdd pmos l=2 w=8mna f a 0 0 nmos l=2 w=4mnb f b 0 0 nmos l=2 w=4.ends or2 *or3.subckt or3 a b c fmorpa 1 a vdd vdd pmos l=2

6、 w=12morpb 2 b 1 vdd pmos l=2 w=12morpc f c 2 vdd pmos l=2 w=12mna f a 0 0 nmos l=2 w=4mnb f b 0 0 nmos l=2 w=4mnc f c 0 0 nmos l=2 w=4.ends or3*or4.subckt or4 a b c d fmorpa 1 a vdd vdd pmos l=2 w=16morpb 2 b 1 vdd pmos l=2 w=16morpc 3 c 2 vdd pmos l=2 w=16morpd f d 3 vdd pmos l=2 w=16mna f a 0 0 n

7、mos l=2 w=4mnb f b 0 0 nmos l=2 w=4mnc f c 0 0 nmos l=2 w=4mnd f d 0 0 nmos l=2 w=4.ends or4*not.subckt not a f mnotpa f a vdd vdd pmos l=2 w=4mnotna f a 0 0 nmos l=2 w=2.ends not *反相器*or21.subckt or21 a b fxor2 a b 1 or2 xnot 1 f not .ends or21 *2輸入或門*or31.subckt or31 a b c fxor3 a b c 1 or3xnot 1

8、f not .ends or31 *3輸入或門 *or41.subckt or41 a b c d fxor4 a b c d 1 or4xnot 1 f not .ends or41 *4輸入或門*xor21.subckt xor21 a b fxm a A5 notxn b B5 notxxor a b A5 B5 f xor2.ends xor21 * 2輸入異或門*and21.subckt and21 a b fxand2 a b 1 and2xnot 1 f not.ends and21 *2輸入與門*and31.subckt and31 a b c fxand3 a b c 1 a

9、nd3xnot 1 f not.ends and31 *3輸入與門*and41.subckt and41 a b c d fxand4 a b c d 1 and4xnot 1 f not.ends and41 *4輸入與門xxor211 a1 b1 p1 xor21 xxor212 a2 b2 p2 xor21xxor213 a3 b3 p3 xor21xxor214 a4 b4 p4 xor21xand211 a1 b1 g1 and21xand212 a2 b2 g2 and21xand213 a3 b3 g3 and21xand214 p1 c0 m0 and21xor211 m0 g

10、1 c1 or21 *進(jìn)位C1xand311 p2 p1 c0 m1 and31xand215 p2 g1 m2 and21xor312 g2 m1 m2 c2 or31 *進(jìn)位C2xand411 p3 p2 p1 c0 m3 and41xand313 p3 p2 g1 m4 and31xand216 p3 g2 m5 and21xor412 m3 m4 m5 g3 c3 or41 *進(jìn)位C3xxor215 p1 c0 s1 xor21 *輸出s1xxor216 p2 c1 s2 xor21 *輸出s2xxor217 p3 c2 s3 xor21 *輸出s3xxor218 p4 c3 s4 x

11、or21 *輸出s4.include "c:lib130nm_bulk.l"tt.opt scale=0.05u.global vdd gndvdd vdd 0 1.2va1 a1 0 pulse 1.2 1.2 20n 1f 1f 30n 100nva2 a2 0 pulse 0 0 20n 1f 1f 30n 100nva3 a3 0 pulse 0 0 20n 1f 1f 30n 100nva4 a4 0 pulse 0 0 20n 1f 1f 30n 100nvb1 b1 0 pulse 1.2 1.2 20n 1f 1f 30n 100n vb2 b2 0 pulse 1.2 1.2 20 1f 1f 30n 100nvb3 b3 0 pulse 0 0 20n 1f 1f 30n