邏輯綜合與時(shí)序仿真課件

Unit4VLSI設(shè)計(jì)方法Chap10邏輯綜合與時(shí)序仿真Unit4VLSI設(shè)計(jì)方法Chap10邏輯綜合與1Unit1緒論

Unit2CMOS電路設(shè)計(jì)基礎(chǔ)

Unit3CMOS電路的邏輯設(shè)計(jì)

Unit4VLSI設(shè)計(jì)方法

Chap8設(shè)計(jì)模式和設(shè)計(jì)流程

Chap9RTL設(shè)計(jì)與仿真

Chap10邏輯綜合與時(shí)序仿真

Chap11可測(cè)試性設(shè)計(jì)與ATPG

Chap12版圖設(shè)計(jì)與驗(yàn)證

Unit1緒論

Unit2CMOS電路設(shè)計(jì)基礎(chǔ)

2SpecificationExecutablemodelRTLcodeGate-levelnetlistCell/interconnectlevelpositionMask-levelgeometrySystem(Behavioral)levelRTLGate(Logic)levelLayout(Physical)Level設(shè)計(jì)階段（設(shè)計(jì)抽象層）設(shè)計(jì)結(jié)果SpecificationSystem(Behaviora3LogicDesign&Simulation:

fromRTL,theninGate-LevelLogicSynthesis得到用已有的基本邏輯單元（庫(kù)單元）互聯(lián)并滿足一定邏輯功能的邏輯構(gòu)成Gate-LevelSimulation（門級(jí)功能仿真與動(dòng)態(tài)時(shí)序分析）一般不做這一步FormalVerification（形式驗(yàn)證）STA（StaticTimingAnalysis，靜態(tài)時(shí)序分析）LogicDesign&Simulation:

4HDLCodingforSynthesis

BasedonSynopsysDesignCompilerHDLCodingforSynthesis

Base5

TheImportanceofQualityofSourceCode

Codesthatarefunctionallyequivalent,butcodeddifferentlywillgivedifferentsynthesisresults.YoucannotrelysolelyonDesignCompilerto“fix”apoorlycodeddesign!Trytounderstandthe“hardware”youaredescribing,togiveDCthebestpossiblestartingpoint.

TheImportanceofQualityof6

ThinkHardware!

WriteHDLhardwaredescriptionsThinkofthetopologyimpliedbythecodeDonotwriteHDLsimulationmodelsNoexplicitdelaysNofileI/O

ThinkHardware!

WriteHDLh7

ThinkSynchronous!

Synchronousdesignsrunsmoothlythroughsynthesis,simulation,test,andlayout

Asynchronousdesignsmayrequirehandinstantiationandextensivesimulationtoverify

Isolateasynchronouslogicintoseparatelycompiledblocks

ThinkSynchronous!

Synchron8

ThinkRTL!

WritinginanRTLcodingstylemeansdescribing:

thecircuittopologytheregisterplacementthefunctionalitybetweenregistersDCoptimizeslogicbetweenregisters:

Itdoesnotoptimizetheregisterplacement

ThinkRTL!

WritinginanRT9

SynthesisofifStatements(1)

Theif-elseconstructimpliesmultiplexinghardwareActualcircuitimplementationdependsontargetlibraryandConstraints

SynthesisofifStatements(1)10

SynthesisofifStatements(2)

Toinferlatches,usean‘if’statementwithoutan‘else’clause

SynthesisofifStatements(2)11

SynthesisofcaseStatements

implyparallelmuxfunction

SynthesisofcaseStatements

12SynthesisofFlip-FlopsSynthesisofFlip-Flops13SynthesisofFlip-FlopsSynthesisofFlip-Flops14Synthesis

BasedonSynopsysDesignCompilerSynthesis

BasedonSynopsysD150.IntroductiontoSynthesis1.Pre-SynthesisProcesses2.ConstrainingtheDesign3.SynthesizingtheDesign0.IntroductiontoSynthesis16

WhatIsSynthesis?

Synthesisisthetransformation

ofanideaintoamanufacturabledevicetocarryoutanintendedfunction.在包含眾多結(jié)構(gòu)、功能、性能均已知的邏輯單元電路的目標(biāo)工藝庫(kù)的支持下得到目標(biāo)工藝庫(kù)中單元電路的連接關(guān)系（邏輯網(wǎng)絡(luò)）的最佳實(shí)現(xiàn)方案滿足設(shè)計(jì)電路的功能要求以及速度、面積等限制條件

WhatIsSynthesis?

Synthesi17

Synthesis’InternalFlow

Synthesis’InternalFlow

18

SynthesisIsConstraint-Driven

SynthesisIsConstraint-Drive19

SynthesisIsPath-Based

SynthesisIsPath-Based

200.IntroductiontoSynthesisPre-SynthesisProcessesTechnologyLibraryforsynthesisDesignHierarchyandPartition2.ConstrainingtheDesign3.SynthesizingtheDesign0.IntroductiontoSynthesis21TechnologyLibrary(1)工藝庫(kù)由Foundary提供，一般是.db的格式，這種格式是DC認(rèn)識(shí)的一種內(nèi)部文件格式，不能由文本方式打開(kāi).db格式可以由文本格式.lib轉(zhuǎn)化過(guò)來(lái)TechnologyLibrary(1)工藝庫(kù)由Foun22

TechnologyLibrary(2)

Duringmapping,DCwill:choose

functionally-correctgatesfromthislibrarycalculatethetimingofthecircuitusingvendor-suppliedtimingdataforthesegates

target_libraryisareservedvariableinDC，youshouldsetittopointtotheTechnologylibraryfile(s)providedbyyoursiliconvendor

TechnologyLibrary(2)

Du23

DesignHierarchy:

RISC_COREexample

DesignHierarchy:

24

DesignHierarchy(Partitioning)

withinHDLDescription

編寫HDL代碼之前（系統(tǒng)設(shè)計(jì)階段）都需要系統(tǒng)劃分，根據(jù)功能或者其他的原則將一個(gè)系統(tǒng)層次化地分成若干個(gè)模塊，這些模塊內(nèi)部再進(jìn)一步細(xì)分成模塊/子模塊Entity(VHDL)andmodule(Verilog)statementsdefinehierarchicalblocks.InferenceofArithmeticCircuits(+,-,*,..)cancreateanewlevelofhierarchy.Process(VHDL)andalways(Verilog)statementsdonotcreatehierarchy

DesignHierarchy(Partitioni25

RepartitioningtoDesignHierarchyforSynthesis

在DC做綜合的過(guò)程中，默認(rèn)的情況下各個(gè)模塊的層次關(guān)系是保留著的。保留著的層次關(guān)系會(huì)對(duì)DC綜合造成一定的影響，比如在優(yōu)化的過(guò)程中，各個(gè)模塊的管腳必須保留，這勢(shì)必影響到模塊邊界的優(yōu)化效果

RepartitioningtoDesignHie26

WhyPartitioning/Repartitioning

PartitioningorRepartitioningisdrivenbymany(oftencompeting)needs:SeparatedistinctfunctionsAchieveworkablesizeandcomplexityManageprojectinteamenvironmentDesignReuseMeetphysicalconstraintsAndmany,manyothers

WhyPartitioning/Repartitio27PoorPartitioning:

soShouldEliminateUnnecessaryHierarchy

PoorPartitioning:

28GoodPartitioning(1):

NoHierarchyinCombinationalPaths

GoodPartitioning(1):

29GoodPartitioning(2):

NoHierarchyinCombinationalPaths

GoodPartitioning(2):

30GoodPartitioning(3):

PartitionatRegisterBoundariesGoodPartitioning(3):

31Example(1):AvoidGlueLogicExample(1):AvoidGlueLogic32Example(2):RemoveGlueLogic

BetweenBlocksExample(2):RemoveGlueLogic33BalanceBlockSizeinPartitioning(1)BalanceBlockSizeinPartitio34BalanceBlockSizeinPartitioning(2)BalanceBlockSizeinPartitio35

Top-LevelDesignPartitioning

Top-LevelDesignPartitioning36

Repartitioningwithin

DesignCompiler

Thegroupandungroupcommandsmodifythepartitionsinadesign.Groupcreatesanewhierarchicalblock.Ungroupremoveseitheroneoralllevelsofhierarchy.

Repartitioningwithin

Design37GroupGroup38UngroupUngroup390.IntroductiontoSynthesis1.Pre-SynthesisProcesses2.ConstrainingtheDesignAreaConstraintsTimingConstraintsandTimeBudgetingEnvironmentalAttributesClockConstraints3.SynthesizingtheDesign0.IntroductiontoSynthesis40

SpecifyingAreaConstraints

施加了一個(gè)最大面積100單位的約束Unitsarethoseoftargetlibrary,definedbythevendor:2-input-NAND-gatetransistorssquaremils

SpecifyingAreaConstraints

41SpecifyTiming

Constraints(1)SynchronousDesigns:DataarrivesfromaclockeddeviceDatagoestoaclockeddeviceObjective:Definethetimingconstraintsforallpathswithinadesign:1.Theinternal(registertoregister)paths2.Allinputpaths3.Alloutputpaths

SpecifyTimingConstraints(1)42SpecifyTiming

Constraints(2)1.Creatingaclockconstrainstimingpathsbetweenregisterscreate_clock-period10[get_portsClk]SpecifyTimingConstraints(2)43SpecifyTiming

Constraints(3)

2.ConstrainingtheInputPaths

set_input_delay–max(inputdelay)–clockClk[get_portsClk]SpecifyTimingConstraints(3)44SpecifyTiming

Constraints(4)

3.ConstrainingOutputPathsset_output_delay–max(outputdelay)–clockClk[get_portsClk]SpecifyTimingConstraints(4)45

TimeBudgeting(1)

Whatifyoudonotknowthedelaysonyourinputsorthesetuprequirementsofyouroutputs?

CreateaTimeBudget!

TimeBudgeting(1)

Whatify46TimeBudgeting(2)TimeBudgetingTimeBudgeting(2)TimeBudgeti47TimeBudgeting:ExampleTimeBudgetingforMY_BLOCKTimeBudgetingforX_BLOCKandY_BLOCK

TimeBudgeting(3)TimeBudgeting:ExampleTimeB48

ConstrainingforTiming:

WhatIsMissing?

輸入輸出的電平轉(zhuǎn)換時(shí)間(transitiontime)由輸入外圍電路的驅(qū)動(dòng)能力和輸出外圍電路的負(fù)載大小決定電路內(nèi)部的互連線時(shí)延的估計(jì)當(dāng)外界溫度或者電路供電電壓發(fā)生變化時(shí)，時(shí)延會(huì)相應(yīng)的改變

ConstrainingforTiming:

Wha49EnvironmentalAttributes(1)set_driving_cell:InputDriveStrengthEnvironmentalAttributes(1)se50EnvironmentalAttributes(2)set_load:OutputCapacitiveLoad

EnvironmentalAttributes(2)se51EnvironmentalAttributes(3)set_wire_load_model:

NetDelaysAWireLoadModel(WLM)isanestimateofanet’sRCparasiticsbasedonthenet’sfanout:ModeliscreatedbyyourvendorEstimatesarebasedonstatisticsfromotherdesignsthevendorhasfabricatedusingthisprocessSpecifyingWLMinDesignCompilerEnvironmentalAttributes(3)se52

EnvironmentalAttributes(4)

OperatingConditionsWhy?Librarycellsareusuallycharacterizedusing“nominal”voltageandtemperature.Ifnot…What?Vendorsallowforsynthesisofcircuitswhichwillnotoperateunder“nominal”conditionsbyembeddingotheroperatingconditionsinthetechnologylibraries

vendor-suppliedoperatingconditions(vendorsmightdelivermultipletechnologylibraries)

EnvironmentalAttributes(4)53OperatingConditions

Tosetoperatingconditions,enterset_operating_conditionscommandDuringsynthesis,“nominal”cellandwiredelayswillbescaledbasedontheoperatingconditionsOperatingConditions54ClockConstraints(1)

RecallTimingConstraintsClockConstraints(1)RecallT55ClockConstraints(2)

對(duì)時(shí)鐘網(wǎng)絡(luò)進(jìn)行綜合時(shí)，需要在時(shí)鐘的各條路徑上要插入大小不一的buffer，目的是為了保證時(shí)鐘到達(dá)每個(gè)觸發(fā)器的時(shí)延盡量相等在定義時(shí)鐘之后，都要給該時(shí)鐘設(shè)置dont_touch，告訴DC不要對(duì)時(shí)鐘網(wǎng)絡(luò)進(jìn)行綜合（插入Buffer）。這是因?yàn)榫C合時(shí)鐘網(wǎng)絡(luò)需要考慮單元的實(shí)際物理位置，這是前端的邏輯綜合（DC）不能完成的工作ClockConstraints(2)對(duì)時(shí)鐘網(wǎng)絡(luò)進(jìn)行綜56ClockConstraints(3)ModelingClockSkew雖然DC無(wú)法最終綜合時(shí)鐘樹(shù)，但是可以加入一些約束讓此時(shí)的時(shí)鐘更加接近實(shí)際的工作情況實(shí)際的時(shí)鐘達(dá)到各個(gè)觸發(fā)器的時(shí)間不是一樣的，它們之間的偏差稱為時(shí)鐘偏差(ClockSkew)。為了反映這個(gè)偏差，我們?cè)诰C合時(shí)可以用一個(gè)命令來(lái)模擬它ClockConstraints(3)Modeling57ClockConstraints(4)ModelingSourceLatency

Clock到達(dá)模塊的端口后，要到達(dá)內(nèi)部的觸發(fā)器，也要經(jīng)過(guò)一定的延時(shí)，這個(gè)延時(shí)稱為NetworkLatencyClockConstraints(4)Modeling580.IntroductiontoSynthesis1.Pre-SynthesisProcesses2.ConstrainingtheDesign3.SynthesizingtheDesignMultipleInstancesHowtoCompileaHierarchicalDesignTimingAnalysisandReport0.IntroductiontoSynthesis59MultipleInstances(1)DesignsInstantiatedMoreThanOnceuniquifycompile+dont_touchMultipleInstances(1)Designs60MultipleInstances(2)uniquifyvs.compile+dont_touchcompile+dont_touch由于只需對(duì)多次例化的模塊編譯一次，可以減少整個(gè)設(shè)計(jì)的編譯時(shí)間，減少內(nèi)存的使用量。在多次例化的模塊很復(fù)雜并且工作站硬件條件有限的情況下，其優(yōu)越性比較明顯。如果這個(gè)Ades是一個(gè)第三方提供的IP硬核(hard-core)，那么也只能使用這種方法在編譯頂層模塊時(shí)，由于Ades設(shè)置了dont_touch，這就妨礙了DC針對(duì)Ades的各個(gè)實(shí)例周圍環(huán)境的不同的進(jìn)一步優(yōu)化，從而使得結(jié)果不能真實(shí)反映各個(gè)實(shí)例周圍的環(huán)境變化Uniquify由于把各個(gè)多例化模塊作為獨(dú)立的模塊來(lái)看，因此DC可以分別針對(duì)它們作出更好的優(yōu)化，從而得到的結(jié)果比較理想編譯的時(shí)間稍微較長(zhǎng)，但是對(duì)于一些不大的模塊來(lái)說(shuō)，這些是可以忽略的。一般推薦使用uniquify解決多例化模塊的綜合問(wèn)題。MultipleInstances(2)uniquify61CompilingaHierarchicalDesign(1)對(duì)一個(gè)大型設(shè)計(jì)來(lái)講，有兩種層次化編譯技術(shù)自上而下(Top-down)將整個(gè)設(shè)計(jì)一次性讀入，施加頂層約束后直接進(jìn)行編譯無(wú)需考慮各個(gè)模塊/子模塊之間的依賴關(guān)系，也就不需要制模塊/子模塊之間的時(shí)序預(yù)算和負(fù)載預(yù)算，都由DC自動(dòng)考慮編寫腳本變得簡(jiǎn)單，維護(hù)起來(lái)也比較方便自下而上(Bottom-up)先單獨(dú)編譯各個(gè)模塊/子模塊：在編譯要考慮與其它模塊之間的關(guān)系，給它們加入時(shí)序預(yù)算和負(fù)載預(yù)算，看是否滿足約束再讀入頂層文件，施加頂層約束，將各個(gè)模塊/子模塊整合起來(lái)：頂層編譯完成后還必須看頂層約束是否滿足CompilingaHierarchicalDesig62CompilingaHierarchicalDesign(2)Pros&ConsofBottom-UpCompile

優(yōu)點(diǎn)利用”分而治之”的策略，對(duì)于大型的不可能一次編譯的設(shè)計(jì)十分有用擺脫了Top-down方法的對(duì)工作站硬件條件的限制，使得大型設(shè)計(jì)也能在一般的機(jī)器上編譯完成

缺點(diǎn)實(shí)現(xiàn)步驟比較多，尤其對(duì)各個(gè)模塊之間的時(shí)序和負(fù)載預(yù)算要求很高SummaryCompilingaHierarchicalDesig63TimingAnalysisandReport(1)WhatTooltoUse?DesignCompilerhasabuilt-instatictiminganalyzercalledDesignTimeTimingAnalysisandReport(1)64TimingAnalysisandReport

(2)

DesignTimeTimingReportsTimingAnalysisandReport(2)65LogicDesign&Simulation:

fromRTL,theninGate-LevelLogicSynthesis得到用已有的基本邏輯單元（庫(kù)單元）互聯(lián)并滿足一定邏輯功能的邏輯構(gòu)成Gate-LevelSimulation（門級(jí)功能仿真與動(dòng)態(tài)時(shí)序分析）一般不做這一步FormalVerification（形式驗(yàn)證）STA（StaticTimingAnalysis，靜態(tài)時(shí)序分析）LogicDesign&Simulation:

66STA

BasedonSynopsysPrimeTimeSTA

BasedonSynopsysPrimeT67WhatisStaticTimingAnalysis?StaticTimingAnalysis（STA）determinesifacircuitmeetstimingconstraintswithoutdynamicsimulation

Threemainsteps:

DesignisbrokendownintosetsoftimingpathsThedelayofeachpathiscalculatedAllpathdelaysarecheckedtoseeiftimingconstraintshavebeenmetWhatisStaticTimingAnalysis68STAStep1:TimingPathsSTAStep1:TimingPaths69Step1實(shí)際是將邏輯電路網(wǎng)表轉(zhuǎn)換成拓?fù)鋱D，圖中的節(jié)點(diǎn)(node)代表電路中的引腳(pin)，節(jié)點(diǎn)之間的邊