eDP-v1.5a-standard原版完整文件

VESAEmbeddedDisplayPort(eDP)Standard

Version1.5aFebruary27,2023

Purpose

ThisStandarddefinesrequirementsandoptionsofastandardizeddisplaypanelinterfaceforembeddeddisplayapplications.ItisbasedonVESADisplayPortStandardVersion2.1(

DPv2.1

or

DPStandard

)andincludesimplementation-specificoptionsrecommendedforconsiderationbythesystemintegrator.

Summary

DPStandard

isascalableandextendablevideodatainterfacedevelopedforuseinbothembedded(internal)andexternal(box-to-box)applications.While

DisplayPort

doesreferenceembeddedapplications,itisprimarilyorientedtowardexternaldisplayinterconnectapplicationswithemphasisoninteroperabilitybetweensystemvendorsandinterconnectcables.ThisStandarddefinesasetoffeaturesforanembeddedversionof

DisplayPort

forapplicationsincluding,butnotlimitedto,laptopsandall-in-onePCs.

Contents

Purpose 1

Summary 1

Preface 16

IntellectualProperty 16

Trademarks 16

SupportforthisStandard 16

Patents 17

Acknowledgments 18

RevisionHistory 20

Section1 Introduction(Informative) 32

Background 32

ExternalConnectionObjectives 32

DocumentOrganization 33

DocumentConventions 35

Precedence 35

Keywords 35

Numbering 35

DPCDRegisterTables 36

UnitofMeasureSymbols 36

AcronymsandAbbreviations 37

Glossary 41

ReferenceDocuments 49

Section2 eDPOverviewandSpecialFeatures(Informative) 51

TypicaleDPSystemImplementation 51

DisplayPortandeDP-specificFeaturesSupported

bySourceandSinkDevices 52

eDPFeaturesandDeviationsfromDisplayPortStandard 53

EnhancedLiveFrameModeOperation 57

Multi-SSTOperationArchitecture 58

HPDandAUX_CHLinkServices 59

DisplayAuthenticationandContentProtectionSupport 59

TPS4BitSequencewhileASSRIsEnabled 66

Adaptive-Sync 74

IgnoreMSAVideoTimingParameters(IgnoreMSA)Option 74

PanelReplay 75

PanelSelfRefresh 75

AdaptiveRefreshPanel 75

UsingDSCandFECineDP 76

Multi-touchovertheAUX_CH 76

eDPInterconnectforVideoData,Power,andBacklightControl 76

DPCDRegistersDefinedbythisStandard 77

Section3 Multi-SSTOperation 82

Introduction 82

MSOTheoryofOperation 82

DPCDRegistersUsedforMSO 85

MSOSourceDeviceConfiguration 86

MSOwithTwoSSTLinks,OneLaneEach(2×1) 88

MSOwithTwoSSTLinks,TwoLanesEach(2×2) 89

MSOwithFourSSTLinks,OneLaneEach(4×1) 91

MSOwithSegmented-panelDisplay(Informative) 93

MSOwithPixelsOverlappingAdjacentPanelSegments 93

TimingMandatesforMSOMain-LinkConfiguration 96

MSOSinkDeviceCRCRegisterUse 96

Section4 eDPElectricalSpecificationExtension 98

Introduction 98

DPCDRegistersUsedforeDPElectricalSpecificationSupport 99

InterconnectReferencePoints 100

Main-LinkTXTP1DifferentialSignalVoltage 102

LinkTraining 102

VDIFFTrainingTable(Informative) 103

Main-LinkElectricalSpecificationTables 107

LinkRatesandJitterBudget 110

RecommendedLinkRates 110

DifferentialNoiseBudget–

LinkRates≤5.4Gbps/lane(HBR2andLower) 111

DifferentialNoiseBudgetandeDPTXParameters–

LinkRates>5.4Gbps/lane(Upto8.1Gbps/lane(HBR3)) 112

JitterBudgetSystem 113

SourceMain-LinkEYEDiagrams 116

TP3_EQEYEMandates 116

TP3_EQReferenceReceiverEqualizers 118

LinkRateDiscoveryandSelection 122

AUX_CH 124

AUX_CHElectricalSub-block 124

AUX_CHTopology 125

HPD 126

LV-HPDSub-block 126

Section5 AdvancedLinkPowerManagement 127

Introduction 127

DPCDRegistersUsedforALPM 129

eDPRXPowerManagementStatesinaDownstreamDevice 130

ALPMSignaling 137

AUX-wakeALPMSignaling 137

AUX-lessALPMSignaling 144

Configuration 153

AUX-wakeDiscovery,Enabling,andDisabling 153

AUX-lessDiscovery,Enabling,andDisabling 153

Section6 PanelSelfRefresh 154

Introduction 154

PSRArchitecture 155

SourceDeviceResponsibilities 157

SinkDeviceResponsibilities 158

PSR1–PanelSelfRefreshVersion1Function 160

PSR1Configuration 160

PSR1FunctionDeviceStates 169

PSR1Entry 175

PSR1ActiveStateandMain-LinkPowerManagement 180

PSR1ExitSequence 187

SingleVideoImageUpdatesduringaPSR1/PSR2ActiveState 189

SinkDeviceDisplayTimingControlduringaPSR1ActiveState 196

VideoFrameTimingRe-synchronizationduringPSR1Exit 197

PSR1ErrorManagementandRecovery 199

DSCUseinthePSR1/PSR2Function 205

PSR2–PanelSelfRefreshVersion2FunctionwithSelectiveUpdate 210

PSR2Configuration 211

PSR2FunctionDeviceStates 223

PSR2Entry 229

PSR2ActiveStateandMain-LinkPowerManagement 234

PSR2ExitSequence 235

SingleVideoImageUpdatesduringaPSR2ActiveState 238

PartialVideoImageUpdateduringaPSR2ActiveState

UsingSelectiveUpdate 238

SinkDeviceDisplayTimingControlduringaPSR2ActiveState 248

VideoFrameTimingRe-synchronizationduringPSR2Exit 250

DSCUseinthePSR2Function 252

CRCDataIntegrityCheckandCorrectiveAction 252

VSCSDPFormatforPSR1/PSR2 253

Section7 AUX_CH-basedSource-to-SinkDeviceActiveVideoImage

TimingSynchronization 258

Introduction 258

DPCDRegistersUsedforAUX_FRAME_SYNC 258

SinkDeviceDeclarationforAUX_FRAME_SYNC 259

AUX_FRAME_SYNCOperation 260

Section8 Adaptive-SyncOperationforVESAAdaptiveSync 265

Introduction 265

DPCDRegistersUsedforAdaptive-Sync 266

FAVTMode 267

AVTMode 267

SourceDeviceAdaptive-SyncOperationMandates 268

SourceDeviceOperationbeforeandduringVideoModeSet 268

SourceDeviceOperationduringLiveFrameTransmission 269

SinkDeviceAdaptive-SyncOperationMandates 275

Adaptive-SyncSDPFormats 276

Section9 PanelReplay 280

Introduction 280

DPCDRegistersUsedforPR 280

ComparisontothePanelSelfRefreshFunction 284

PREnumerationandConfiguration 284

PRStates 285

DSCUseinthePRFunction 291

DSCPPSSDPContentChangebetweenLiveFrameModeandPR 292

Compressed-to-UncompressedVideoChangebetween

LiveFrameModeandPR 292

DSC_CRC_xTestOperation 292

PRwithMain-LinkTurnedON 293

SUinPRwithMain-LinkTurnedON 293

PRConcurrentwithALPM 293

VideoTimingSynchronizationwhileinaPRActiveState

withALPMEnabled 293

TransitionbetweenLiveFrameModeandPRwithALPMEnabled 296

PRwithoutaLiveActiveVideoImagePixelDataUpdate 297

Full-screenLiveActiveVideoImageUpdateinPR 297

SUinPRwithALPMMode 299

VSCSDPFormatforPR 302

Section10 AdaptiveRefreshPanel 305

Introduction 305

DPCDRegistersUsedforARP 306

ModesofOperation 307

PollingMode 307

InterruptMode 309

Section11 CompressedDisplayStreamTransportServicesandFEC 311

Introduction 311

DPCDRegistersUsedforDSCandFEC 311

DSCImplementation 312

DSCVersionUsage 312

SinkDeviceConfiguration 312

Slices/Line 312

DSCUseinthePSR1,PSR2,andPRFunctions 313

VSCSDPinDSCConfiguration 313

PRandPSR2SelectiveUpdateinDSCConfiguration 314

CRCUsagewithDSCduringPSRorPR 315

SourceDevice-sideCRCGeneration 315

SinkDevice-sideDSCCalculation 316

FECOperation 318

Section12 Multi-touchoverAUX_CH 319

Introduction 319

DPCDRegistersUsedforMulti-touch 320

MandatesandScope 321

DeviceDiscovery 323

CapabilityDiscovery 323

BootMode 323

SinkDeviceConfiguration 324

RegisterLayoutandAccessMandates 327

HIDClassDescriptors 327

HIDReportDescriptors 328

HIDReportsLayout 329

DataTransfer 331

SourceDeviceInterrupt-basedDataAccesstoInputorFeatureReport 331

SourceDevicePolledDataAccesstoInputorFeatureReport 333

CombinationofSourceDeviceInterrupt-basedandPolledDataAccess 334

SourceDeviceDataAccesstoOutputReport 334

SinkDeviceDataAccesstoFeatureReport 336

ReportFreshness 336

ConcurrencyDefinition 337

ConcurrencyofTouchwithKeyboard 337

ConcurrencyofTouchwithMouse 337

ConcurrencyofTouchwithKeyboardandMouse 339

SinkDeviceLimitationRegardingMultipleKeyboard

orMouseFunctions 339

eDPTouchExample(Informative) 340

HIDDescriptor 340

ReportDescriptor 341

REPORT_DATALayout 344

Section13 eDPDisplayControl 345

DPCDRegistersUsedforDisplayControl 345

DisplayBacklightControlUsingDPCDRegisters 348

DisplayPanelSelf-Test(Informative) 358

Section14 DisplayPowerSequencing 360

DPCDRegistersUsedforDisplayPowerSequencing 360

eDPInterfacePower-onandPower-offSequences 360

DisplayPowerSequencingCapabilities 363

Section15 eDPConnectorPinAssignments(Informative) 364

Section16 eDPRegisters 370

DPCDFieldAddressMapping 370

Registers/RegisterDifferencesUniquetoeDP 371

AppendixA LaneRate/Countvs.SupportedPixelBandwidth(Informative) 428

NumberofMain-LinkLanesvs.VideoModeSupport 428

AppendixB ElectricalSpecificationDevelopment(Informative) 430

Introduction 430

End-to-EndDescription 430

eDPTXI/OAssumptions 431

End-to-EndChannelEYEMask,RX_EQ 432

HBR3ReferenceChannels 433

ReferenceCableModels 434

ReferenceSourceRouteModels 436

ReferenceSinkRouteModels 439

AppendixC

MainContributorHistory(PreviousVersions) 441

Tables

Table1: Patents 17

Table2: MainContributorstoeDPv1.5a 18

Table3: RevisionHistory 20

Table1-1: Keywords 35

Table1-2: Numbering 35

Table1-3: UnitofMeasureSymbols 36

Table1-4: AcronymsandAbbreviations 37

Table1-5: Glossary 41

Table1-6: ReferenceDocuments 49

Table2-1: eDPFeaturesandMandatesthatDifferfromDPStandard 53

Table2-2: OptionaleDPDisplayAuthenticationandContentProtectionMethods 60

Table2-3: ExpandedProcessStepsofFigure2-7 65

Table2-4: eDPDPCDRegisterAddressMappingDeviationsfromDPStandard 77

Table3-1: DPCDRegistersUsedforMSO 85

Table3-2: MSOSourceDeviceLinkConfigurations 86

Table3-3: MSOLinkDPCDRegisterMatrix 97

Table4-1: DPCDRegistersUsedforeDPElectricalSpecificationSupport 99

Table4-2: InterconnectReferencePoints 100

Table4-3: RecommendedTP1DifferentialSignalVoltages 102

Table4-4: GenericTrainingTable 103

Table4-5: LowVDIFFTrainingTableExample 103

Table4-6: HighVDIFFTrainingTableExample 103

Table4-7: SingleVDIFFTrainingTableExample 104

Table4-8: SingleNon-transitionVDIFFp-pwithVariableTransitionVDIFFp-pExample 105

Table4-9: StretchedeDPTrainingTableExample 105

Table4-10: eDPv1.3-compatibleTrainingTableExample 106

Table4-11: RecommendedSourceMain-LinkTXElectricalSpecifications 107

Table4-12: RecommendedSinkMain-LinkRXElectricalSpecifications 109

Table4-13: RecommendedLinkRates 110

Table4-14: DifferentialNoiseBudgetinUI–LinkRates≤5.4Gbps/lane(HBR2andLower) 111

Table4-15:eDPTXReferenceReceiverCTLEandReferenceReceiverCTLE+Reference

ReceiverDFETPE_EQParameters–LinkRates>5.4Gbps/lane

(Upto8.1Gbps/lane(HBR3) 112

Table4-16: JitterBudgetApplicationofRecommendedLinkRates1through7 113

Table4-17: 4.155Gbps/laneCustomLinkRateJitterBudgetExample 114

Table4-18: 2.0775Gbps/laneCustomLinkRateJitterBudgetExample 114

Table4-19: 2.496Gbps/laneCustomLinkRateJitterBudgetExample 115

Table4-20: 1.456Gbps/laneCustomLinkRateJitterBudgetExample 115

Table4-21: TP3_EQEYEMandates 116

Table4-22: TP3_EQEYEMaskVertices–LinkRates≤5.4Gbps/lane(HBR2andLower) 117

Table4-23: TP3_EQEYEMaskVertices–LinkRates>5.4Gbps/lane

(Upto8.1Gbps/lane(HBR3))forSinkDeviceswithReferenceReceiverCTLE 117

Table4-24:TP3_EQEYEMaskVertices–LinkRates>5.4Gbps/lane

(Upto8.1Gbps/lane(HBR3))forSinkDeviceswith

ReferenceReceiverCTLE+ReferenceReceiverDFE 117

Table4-25: TP3_EQReferenceReceiverEqualizerPolesand0s–

LinkRates≤5.4Gbps/lane(HBR2andLower) 119

Table4-26: LinkRateDiscovery/SelectionMethodInteroperabilitySummary 123

Table4-27: RecommendedAUX_CHParametersthatDifferfromtheDPStandardSpecification 124

Table4-28: eDPLV-HPDElectricalSpecificationsatTP3 126

Table5-1: DPCDRegistersUsedforALPM 129

Table5-2: PowerManagementStates 130

Table5-3: AUX-wakeALPMML_PHY_SLEEPandML_PHY_STANDBY

SequenceK-codeDefinitions 137

Table5-4: AUX-wakeALPMFastWakeTimingParameters 141

Table5-5: AUX-lessALPMML_PHY_SLEEPSequenceK-codeDefinition 144

Table5-6: AUX-lessALPMLFPSSignalingParameters 149

Table5-7: AUX-lessALPMPHYEstablishmentandACDSPeriodTimingParameters 151

Table6-1: PSRFunctionMain-LinkActivityOptions 154

Table6-2: SummaryofDPCDRegistersUsedforPSR1–

PSR1CapabilityDeclarationbySinkDevice 161

Table6-3: SummaryofDPCDRegistersUsedforPSR1–PSR1ConfigurationforSinkDevice 164

Table6-4: VSCSDPPSR1CommandSummary 166

Table6-5: SummaryofDPCDRegistersUsedforPSR1–PSR1SinkDeviceStatusIndications 167

Table6-6: SourceDevicePSR1States 170

Table6-7: SinkDevicePSR1States 173

Table6-8: SinkDeviceActionforSingleVideoImageUpdate 191

Table6-9: VSCSDPByteMapUsedforPSR1/PSR2,withBitstream 206

Table6-10: SummaryofDPCDRegistersUsedforPSR2–

PSR2CapabilityDeclarationbySinkDevice 212

Table6-11: SummaryofDPCDRegistersUsedforPSR2–PSR2ConfigurationforSinkDevice 216

Table6-12: VSCSDPPSR2CommandSummary 219

Table6-13: SummaryofDPCDRegistersUsedforPSR2–PSR2SinkDeviceStatusIndications 221

Table6-14: SourceDevicePSR2States 224

Table6-15: SinkDevicePSR2States 227

Table6-16: ValidPSR2VSCSDPControlBitSettingCombinations 246

Table6-17: SinkDeviceVideoTimingOptionsduringaPSR2ActiveState 248

Table6-18: VSCSDPByteMapUsedforPSR1/PSR2 253

Table6-19: VSCSDPHeaderExtensionforthePSR1/PSR2Functions 254

Table6-20: VSCSDPPayloadExtensionforthePSR1/PSR2Function 255

Table7-1: DPCDRegistersUsedforAUX_FRAME_SYNC 258

Table7-2: AllowedGTCExceptionsforAUX_FRAME_SYNC 262

Table8-1: DPCDRegistersUsedforAdaptive-Sync 266

Table8-2: Adaptive-SyncSDPHeaderBytes 276

Table8-3: Adaptive-SyncSDPVersion2PayloadDataBytes 277

Table9-1: DPCDRegistersUsedforPR 281

Table9-2: PSRFunctionMain-LinkActivityOptions 284

Table9-3: SourceDevicePRStates 286

Table9-4: SinkDevicePRStates 289

Table9-5: eDPDSCSinkDeviceCompressedTransportBitRateRange 291

Table9-6: Adaptive-Sync

SDPSetupTimeConfigurationduringPR_State2(Active) 295

Table9-7: Adaptive-Sync

SDPSetupTimeduringPR_State2(Active)

whenDPCD0011Ah[7:6]=01b 295

Table9-8: VSCSDPHeaderExtensionBytesforthePRFunction 302

Table9-9: VSCSDPPayloadExtensionBytesforthePRFunction 303

Table10-1: DPCDRegistersUsedforARP 306

Table10-2: ARPTimingParametersUsedinFigure10-3 310

Table11-1: DPCDRegistersUsedforDSCandFEC 311

Table11-2: VSCSDPByteMapwithBitstream 313

Table12-1: DPCDRegistersUsedforMulti-touch 320

Table12-2: TouchSinkDeviceConfigurationBits 324

Table12-3: Touch-basedDeviceModes–ConcurrencyofTouchwithMouse 338

Table12-4: Touch-basedDeviceModes–ConcurrencyofTouchwithKeyboardandMouse 339

Table13-1: DPCDRegistersUsedforDisplayControl 345

Table13-2: DisplayControlCapabilities 346

Table13-3: BacklightBrightnessBitLocationswhenDPCD00702h[2]=0

andDPCD00703h[2:1]=01b 350

Table13-4: BacklightBrightnessBitLocationswhenDPCD00702h[2]=0

andDPCD00703h[2:1]=10b 351

Table13-5: BacklightBrightnessBitLocationswhenDPCD00702h[2]=1

andDPCD00703h[2:1]=01b 352

Table13-6: BacklightBrightnessBitLocationswhenDPCD00702h[2]=1

andDPCD00703h[2:1]=10b 353

Table13-7: SummaryofBacklightControlModesUsingDPCDRegistersListedinTable13-1 355

Table13-8: DisplaySelf-TestColorSquareDefinition 358

Table14-1: DPCDRegistersUsedforDisplayPowerSequencing 360

Table14-2: eDPInterfacePowerSequenceTimingParametersUsedinFigures

14-1and14-2 362

Table14-3: DisplayPowerSequencingCapabilities 363

Table15-1: 20-PineDPPinAssignmentforCCFLBacklight

(1-or2-laneeDP) 365

Table15-2: 30-PineDPPinAssignmentforLEDBacklightwithoutLEDDriveronPCB

(1-or2-laneeDP) 366

Table15-3: 30-PineDPPinAssignmentforLEDBacklightwithLEDDriveronPCB

(1-or2-laneeDP) 367

Table15-4: 40-PineDPPinAssignmentforLEDBacklightwithLEDDriveronPCB

(upto4-laneeDP) 368

Table16-1: DPCDFieldAddressMapping 370

Table16-2: eDPAddressMappingwithinDPCDReceiverCapabilityField

(DPCD00000hthrough000FFh) 371

Table16-3: eDPAddressMappingwithinDPCDLinkConfigurationField

(DPCD00100hthrough001FFh) 380

Table16-4: eDPAddressMappingwithinDPCDLink/SinkDeviceStatusField

(DPCD00200hthrough002FFh) 389

Table16-5: eDPAddressMappingwithinDPCDeDP-specificField

(DPCD00700hthrough007FFh) 391

Table16-6: eDPAddressMappingwithinDPCDeDPRXEventStatusIndicatorField

(DPCD02000hthrough021FFh) 414

Table16-7: eDPAddressMappingwithinDPCDExtendedReceiverCapabilityField

(DPCD02200hthrough022FFh) 421

Table16-8: eDPAddressMappingwithinDPCDMulti-touch(foreDP)Field

(DPCD60000hthrough61CFFh) 423

TableA-1: SupportedVideoModeExamplesforCommoneDPConfigurations 429

TableB-1: eDPAnalysisParameters 431

TableB-2: eDPTXI/OAssumptions 431

TableB-3: eDPRX_EQEYEMaskVertices 432

TableB-4: ReferenceCableModelParameters 434

TableB-5: ReferenceCableModelLengthsandModelNames 434

TableB-6: ReferenceSourceRouteModelParameters 437

TableB-7: ReferenceSourceRouteModelLengthsandModelNames 437

TableB-8: ReferenceSinkRouteModelParameters 439

TableB-9: ReferenceSinkRouteModelLengthsandModelNames 439

TableC-1: MainContributorHistory(PreviousVersions) 441

Figures

Figure2-1: TypicaleDPSystemImplementation 51

Figure2-2: MSOExampleDrivingaDisplaywithFourSegments 58

Figure2-3: ExampleofOneeDPPanelSupportingMultipleSourceDevice

DisplayAuthenticationMethods 62

Figure2-4: eDPPanelFactoryProductionProcessOperationalExample 62

Figure2-5: eDPPanelEmbeddedinLaptopOperationalExample 63

Figure2-6: eDPPanelFieldServiceProcessOperationalExample 63

Figure2-7: Method3aIdentificationandControlduringLinkTrainingSequence 64

Figure3-1: eDPvs.eDPMSOComparison(Informative) 84

Figure3-2: eDPMSOwithTwoSSTLinks,OneLaneEach 88

Figure3-3: DivisionofPixelsinaTwo-SSTLinkSystemDrivingTwoPanelSegments–

2×1Configuration 88

Figure3-4: eDPMSOwithTwoSSTLinks,TwoLanesEach 89

Figure3-5: DivisionofPixelsinaTwo-SSTLinkSystemDrivingTwoPanelSegments–

2×2Configuration 90

Figure3-6: eDPMSOwithFourSSTLinks,OneLaneEach 91

Figure3-7: DivisionofPixelsinaFour-SSTLinkSystemDrivingFourPanelSegments–

4×1Configuration 92

Figure3-8: PixelOverlapUsingMSOwithTwoSSTLinks 94

Figure3-9: PixelOverlapUsingMSOwithFourSSTLinks 95

Figure4-1: EmbeddedLinkReferencePoints(Informative) 101

Figure4-2: TP3_EQ(Informative) 101

Figure4-3: TopologywithoutTP3(Informative) 101

Figure4-4: TP3_EQEYEMask 116

Figure4-5: TP3_EQReferenceReceiverEqualizerTransferFunctions–

LinkRates≤5.4Gbps/lane(HBR2andLower) 119

Figure4-6: ReferenceReceiverCTLEforTP3_CTLECurves–

LinkRates>5.4Gbps/lane(Upto8.1Gbps/lane(HBR3)) 120

Figure4-7: ReferenceReceiverEqualizerforReferenceReceiverCTLE+

ReferenceReceiverDFE–LinkRates>5.4Gbps/lane

(Upto8.1Gbps/lane(HBR3)) 121

Figure4-8: RecommendedeDPAUX_CHTopology 125

Figure5-1: SinkDevicePMStateDiagram 128

Figure5-2: AUX-wakeALPMAUX_PHY_WAKESignal 139

Figure5-3: AUX-wakeALPMAUX_PHY_WAKE_ACKSignal 139

Figure5-4: AUX-wakeALPMFastWakeTimingRelationships 141

Figure5-5: AUX-wakeALPMCombinedAUX_PHY_WAKEwithAUXTransaction

fromSourceDevice 142

Figure5-6: AUX-wakeALPMCombinedAUXWake/TransactionTimingRelationships 143

Figure5-7: AUX-lessALPMLinkPower-offTransmissionInitiatedbySourceDevice 144

Figure5-8: AUX-lessALPMML_PHY_WAKESignaling 147

Figure5-9: AUX-lessALPMLFPSSignaling 148

Figure5-10: AUX-lessALPMTransitionfromML_PHY_LOCKSignal

toVideoStreamTransmission 152

Figure6-1: PSRSystem-LevelDiagram 155

Figure6-2: PictorialRepresentationofVideoFrameandActiveVideoImage 156

Figure6-3: PSR1Configuration 163

Figure6-4: SourceDevicePSR1States 169

Figure6-5: SinkDevicePSR1States 172

Figure6-6: RFBCaptureofActiveVideoImageinVideoFrameN 176

Figure6-7: RFBCaptureofActiveVideoImageinVideoFrameN+1 176

Figure6-8: PSR1EntryAbortinVideoFrameN+1 178

Figure6-9: PSR1EntryAbortinVideoFrameN+2 179

Figure6-10: PSR1Main-LinkOFFTimingwhenRFBCapture

ofActiveVideoImageIsinVideoFrameN 181

Figure6-11: PSR1Main-LinkOFFTimingwhenRFBCapture

ofActiveVideoImageIsinVideoFrameN+1 182

Figure6-12: PSR1SequenceofTurningONtheMain-LinkwithoutLinkTraining 183

Figure6-13: PSR1Main-LinkONManagement 184

Figure6-14: PSR1ExitSetupTimetoFirstCapturedActiveVideoImage 187

Figure6-15: SingleVideoImageUpdateOption1–VSCSDPwithDB1[1]Indication 190

Figure6-16: SingleVideoImageUpdateOption2–UsingTwoVSCSDPs 190

Figure6-17: PSR1/PSR2SingleVideoImageUpdatewhentheMain-LinkIsTurnedOFF 192

Figure6-18: SingleVideoImageUpdateImmediatelyfollowingPSR1/PSR2Entry 193

Figure6-19: SingleVideoImageUpdateTimingwithOptionalVSCSDPforPSR1/PSR2Exit 194

Figure6-20: BurstSingleVideoImageUpdateVSCSDPTiming 195

Figure6-21: CRCVSCSDPTimingwithDPCD00170h[3]=0

andforSingleVideoImageUpdate 202

Figure6-22: CRCVSCSDPTimingwithDPCD00170h[3]=1 203

Figure6-23: SourceDevice-sideCRCComponentLocations

fortheBitstream(CompressedPixelStream) 208

Figure6-24: SinkDevice-sideCRCComponentLocations

fortheBitstream(CompressedPixelStream) 209

Figure6-25: ConceptualDiagramofPSR2inUse 210

Figure6-26: PSR2Configuration 215

Figure6-27: SourceDevicePSR2States 223

Figure6-28: SinkDevicePSR2States 226

Figure6-29: RFBCaptureofActiveVideoImageinVideoFrameN 230

Figure6-30: RFBCaptureofActiveVideoImageinVideoFrameN+1 230

Figure6-31: PSR2EntryAbortinVideoFrameN+1 232

Figure6-32: PSR2EntryAbortinVideoFrameN+2 233

Figure6-33: PSR2ExitSetupTimetoFirstCapturedActiveVideoImage 236

Figure6-34: PSR2SUTimingDiagram 242

Figure6-35: PSR2TimingduringSURegion(Informative) 243

Figure6-36: PSR2FunctionduringSURegionEarlyTransport 245

Figure7-1: AUX_FRAME_SYNC 261

Figure8-1: Adaptive-SyncSDPTransmissionTiming 269

Figure8-2: FAVT_120-to-FAVT_48Transitionwith4.25-msVideoFrameDuration

IncreaseandDecreaseConstraint 272

Figure8-3: FAVT_120-to-FAVT_48TransitionwithoutVideoFrameDuration

IncreaseorDecreaseConstraints 273

Figure8-4: FAVT-to-AVTTransitions 274

Figure9-1: SourceDevicePRStates 285

Figure9-2: SinkDevicePRStates 288

Figure9-3: PREntryandExitVideoFrames 296

Figure9-4: PRSUwithALPMConfiguration 300

Figure10-1: ARP-capableeDPSystem 305

Figure10-2: TimingofPollingRegisterwithRespecttoActiveVideoImage 308

Figure10-3: ARPInterruptTimingDiagram 310

Figure11-1: SUwithDSC 314

Figure11-2: SourceDevice-sideCRCComponentLocations

fortheBitstream(CompressedPixelStream) 315

Figure11-3: SinkDevice-sideCRCComponentLocations

fortheBitstream(CompressedPixelStream) 316

Figure12-1: HIDoverAUX_CH 321

Figure12-2: HID_CLASS_DESCRIPTORSDPCDRegionLayout 327

Figure12-3: REPORT_DATADPCDRegionLayout 329

Figure12-4: OUTPUT_REPORTDPCDRegionLayout 330

Figure12-5: Interrupt-basedDataAccessSequence 331

Figure12-6: PolledDataAccessSequence 333

Figure12-7: OutputReportCommunicationSequence 334

Figure12-8: ExampleFeatureandInputReportsinREPORT_DATAArea 344

Figure13-1: SystemBlockDiagramofBacklightBrightnessControlthroughAUX_CH 348

Figure13-2: TCONCircuitBlocksDeterminePanelBacklightFrequency 356

Figure13-3: DisplayPanelSelf-TestPatterns 358

Figure14-1: eDPInterfacePower-on/Power-offSequence–NormalSystemOperation 361

Figure14-2: eDPInterfacePower-on/Power-offSequence–AUXTransactionOnly 361

FigureB-1: End-to-endChannelInterconnect 431

FigureB-2: eDPRX_EQEYEMask 432

FigureB-3: ReferenceCableModels–ModelSeries1 434

FigureB-4: ReferenceCableModels–ModelSeries2 434

FigureB-5: ReferenceCableModels–DifferentialInsertionLoss 435

FigureB-6: ReferenceCableModels–DifferentialReturnLoss 435