FLASH370i_系列CPLD芯片介紹（中英文翻譯）.doc

FLASH370i系列CPLD芯片介紹這篇應(yīng)用說(shuō)明書(shū)涵蓋以下內(nèi)容：（1）對(duì)復(fù)雜可編程邏輯器件（CPLD）的綜合描述；（2）對(duì)FLASH370i系列器件的總體介紹。CPLD 簡(jiǎn)介空間占用更少，性能提高，費(fèi)用降低，CPLD這些因素使其將PLD的概念擴(kuò)展到一個(gè)更高性能的水平上。在結(jié)構(gòu)上，CPLD是由大量的可編程邏輯器件（PLD）及邏輯陣列塊（LAB）組成的，這些結(jié)構(gòu)通過(guò)可編程內(nèi)部矩陣（PIM）連接在一起。因此CPLD性能的提高并非是通過(guò)增加輸入項(xiàng)與乘積項(xiàng)的數(shù)量，增大體積來(lái)實(shí)現(xiàn)的。大量的邏輯陣列塊（LAB）提供了與PLD可相比擬的速度，因?yàn)榛镜膫鬏斅窂绞峭ㄟ^(guò)一個(gè)邏輯陣列塊而且各個(gè)的乘積項(xiàng)矩陣與PLD矩陣相當(dāng)。大量的LAB也提供了更高的集成度。一個(gè)CPLD所包含的LABs根據(jù)其大小，通常介于2到16之間。LABs除了由PIM連接之外，也由輸入與輸出宏單元及專用輸入宏單元相連。圖1，2分別為CPLD的總構(gòu)成圖與內(nèi)部LB的結(jié)構(gòu)圖。LAB的結(jié)構(gòu)元件包括：（1）陣列；（2）分配器；（3）宏單元。CPLD中的乘積項(xiàng)矩陣與PLD中的乘積項(xiàng)矩陣一樣，所不同之處在于，前者的輸入也可以是來(lái)自于PIM。乘積項(xiàng)分配器是CPLD中的一個(gè)新概念，在CPLD中乘積項(xiàng)并非是通過(guò)輸入與輸出引腳固定與宏單元的，而是能根據(jù)需要聯(lián)到不同的宏單元上。這樣的結(jié)果是更加有效的乘積項(xiàng)分配與更高的集成度。根據(jù)CPLD的不同，乘積項(xiàng)分配器的應(yīng)用也不相同，這些將在FLASH370i系列器件特性一結(jié)中加以講述。宏單元接收單個(gè)的乘積項(xiàng)分配器提供的輸入，即數(shù)量不確定的乘積項(xiàng)相或。在一些宏單元中，輸入信號(hào)與另一個(gè)可能是Q端回饋的信號(hào)進(jìn)入一個(gè)二輸入的異或門。這樣便將D觸發(fā)器配置成T觸發(fā)器，對(duì)于如計(jì)數(shù)器等某些設(shè)計(jì)，后者將使其獲得性能上的提高。經(jīng)過(guò)異或門之后，宏單元可被配置成寄存器型，組合邏輯型或鎖存型。有兩種類型的宏單元，輸入/輸出型與隱藏型。一些特殊的宏單元不僅輸入到輸入/輸出型宏單元而且也反饋到乘積項(xiàng)矩陣。隱藏型宏單元僅為乘積項(xiàng)矩陣提供反饋信號(hào)。PIM的功能是將可用資源的需要部分，所有來(lái)自LAB的輸出及某些輸入輸出引腳分派給適當(dāng)?shù)腖AB。有兩種PIM的應(yīng)用方法：矩陣型的連接與乘積項(xiàng)型的連接。圖3顯示了基于矩陣型連接的兩個(gè)LAB之間的數(shù)據(jù)傳輸。在矩陣型的連接中，LAB的每個(gè)輸出可以通過(guò)一存儲(chǔ)單元聯(lián)結(jié)到任意個(gè)輸入項(xiàng)中。每個(gè)PIM輸入項(xiàng)被指定到一個(gè)特殊的LAB或功能中作為L(zhǎng)AB乘積項(xiàng)矩陣的輸入信號(hào)。在本示例中，只顯示了四個(gè)PIM輸入項(xiàng)，兩個(gè)進(jìn)入LAB1，兩個(gè)進(jìn)入LAB2。每一個(gè)輸入項(xiàng)都有一個(gè)感受器，可以探測(cè)邏輯電平，緩沖信號(hào)，提供驅(qū)動(dòng)。由于每一個(gè)LAB輸出可以聯(lián)接到任意的PIM輸入，內(nèi)部連接是100%可連通的。而且絕不會(huì)限制器件適配邏輯的能力。一個(gè)宏單元的輸出可以能夠聯(lián)接到一個(gè)或多個(gè)PIM輸入項(xiàng)。與基于選擇型的連接方式相比，將存儲(chǔ)單元作為連接的最大不足之處是傳輸延遲。圖4描述了基于選擇型連接的兩個(gè)LABS之間的數(shù)據(jù)通信通道。在多路選擇型連接中，選擇器將多個(gè)PIM輸入項(xiàng)中的一個(gè)送入LAB。PIM輸入項(xiàng)不同于矩陣型連接之處在于，他們是從n（n指輸入的選擇器的數(shù)目）個(gè)選擇器中的一個(gè)輸入的，而非是一個(gè)或門存儲(chǔ)陣列的輸出。進(jìn)入選擇器的輸入是所有的LAB輸出及特殊的輸入端與輸入/輸出引腳。圖3示出了由兩個(gè)4-1選擇器產(chǎn)生的兩路PIM輸入項(xiàng)。在這個(gè)例子里，LAB1中的宏單元2與LAB2中的宏單元2都有兩種進(jìn)入選擇器的可能，其他的輸入僅有一種。選擇器越寬（選擇器輸入的數(shù)目），所需進(jìn)入每個(gè)LAB的輸入將成功布通，每個(gè)信號(hào)布通到LAB的可能性也越大。選擇器變寬的劣勢(shì)在于通過(guò)PIM的傳輸延遲增加，也增大了結(jié)構(gòu)尺寸。基于選擇型連通結(jié)構(gòu)的應(yīng)用因選擇器規(guī)模而不同。FLASH370i型CPLDS的特點(diǎn)FLASH370i型CPLDS提供了從2個(gè)到8個(gè)LABs的密度。圖5顯示了有8個(gè)LABs的CY7C374i/5i結(jié)構(gòu)圖。偶數(shù)型的器件將一半的宏單元隱藏，使得在引腳一定的情況下獲得最大的集成度。表1示例了一些器件。CPLD是屬于粗粒結(jié)構(gòu)的可編程邏輯器件。它具有豐富的邏輯資源(即邏輯門與寄存器的比例高)和高度靈活的路由資源。CPLD的路由是連接在一起的，而FPGA的路由是分割開(kāi)的。FPGA可能更靈活，但包括很多跳線，因此速度較CPLD慢。 CPLD以群陣列（array of clusters）的形式排列，由水平和垂直路由通道連接起來(lái)。這些路由通道把信號(hào)送到器件的引腳上或者傳進(jìn)來(lái)，并且把CPLD內(nèi)部的邏輯群連接起來(lái)。CPLD之所以稱作粗粒，是因?yàn)?，與路由數(shù)量相比，邏輯群要大得到。CPLD的邏輯群比FPGA的基本單元大得多，因此FPGA是細(xì)粒的.CPLD的功能塊 CPLD最基本的單元是宏單元。一個(gè)宏單元包含一個(gè)寄存器(使用多達(dá)16個(gè)乘積項(xiàng)作為其輸入)及其它有用特性。 因?yàn)槊總€(gè)宏單元用了16個(gè)乘積項(xiàng)，因此設(shè)計(jì)人員可部署大量的組合邏輯而不用增加額外的路徑。這就是為何CPLD被認(rèn)為是“邏輯豐富”型的。 宏單元以邏輯模塊的形式排列(LB)，每個(gè)邏輯模塊由16個(gè)宏單元組成。宏單元執(zhí)行一個(gè)AND操作，然后一個(gè)OR操作以實(shí)現(xiàn)組合邏輯。每個(gè)邏輯群有8個(gè)邏輯模塊，所有邏輯群都連接到同一個(gè)可編程互聯(lián)矩陣。 每個(gè)群還包含兩個(gè)單端口邏輯群存儲(chǔ)器模塊和一個(gè)多端口通道存儲(chǔ)器模塊。前者每模塊有8，192b存儲(chǔ)器，后者包含4，096b專用通信存儲(chǔ)器且可配置為單端口、多端口或帶專用控制邏輯的FIFO。 CPLD的好處之一是在給定的器件密度上可提供更多的I/O數(shù)，有時(shí)甚至高達(dá)70%。 時(shí)序模型簡(jiǎn)單 CPLD優(yōu)于其它可編程結(jié)構(gòu)之處在于它具有簡(jiǎn)單且可預(yù)測(cè)的時(shí)序模型。這種簡(jiǎn)單的時(shí)序模型主要應(yīng)歸功于CPLD的粗粒度特性。 CPLD可在給定的時(shí)間內(nèi)提供較寬的相等狀態(tài)，而與路由無(wú)關(guān)。這一能力是設(shè)計(jì)成功的關(guān)鍵，不但可加速初始設(shè)計(jì)工作，而且可加快設(shè)計(jì)調(diào)試過(guò)程。 粗粒CPLD結(jié)構(gòu)的優(yōu)點(diǎn) CPLD是粗粒結(jié)構(gòu)，這意味著進(jìn)出器件的路徑經(jīng)過(guò)較少的開(kāi)關(guān)，相應(yīng)地延遲也小。因此，與等效的FPGA相比，CPLD可工作在更高的頻率，具有更好的性能。 CPLD的另一個(gè)好處是其軟件編譯快，因?yàn)槠湟子诼酚傻慕Y(jié)構(gòu)使得布放設(shè)計(jì)任務(wù)更加容易執(zhí)行。 圖6，7顯示了乘積項(xiàng)矩陣，乘積項(xiàng)分配器，宏單元，及FLASH370i系列器件的輸入/輸出宏單元。每個(gè)LAB有36個(gè)輸入，這使得其足可以處理32位的運(yùn)算。80個(gè)標(biāo)準(zhǔn)的乘積項(xiàng)被提供給乘積項(xiàng)分配器，乘積項(xiàng)分配器可以為16個(gè)宏單元中的每一個(gè)分配0到16個(gè)乘積項(xiàng)。此外，6個(gè)特殊的乘積項(xiàng)也由乘積項(xiàng)矩陣生成。他們是一個(gè)異步復(fù)位，異步置位，和兩組的乘積項(xiàng)輸出使能。輸出宏單元（圖8）提供一組4輸出控制選項(xiàng)：（1）來(lái)自一個(gè)輸出使能（2）來(lái)自另一個(gè)輸出使能的控制，（3）一直使能控制，（4）一直不使能控制。每一個(gè)LAB包含4個(gè)輸出使能乘積項(xiàng)，兩個(gè)控制上面的8個(gè)宏單元，另兩個(gè)控制下面的8個(gè)宏單元。狀態(tài)宏單元（圖8）含有寄存器，觸發(fā)器，或是組合電路傳輸數(shù)據(jù)的選擇項(xiàng)。對(duì)于輸入輸出宏單元，另有一個(gè)輸出優(yōu)先級(jí)選擇器在信號(hào)到達(dá)輸入/輸出宏單元前來(lái)提高性能。對(duì)于隱藏型宏單元，另有一個(gè)選擇器可以將狀態(tài)寄存器配置成一個(gè)輸入寄存器。如果隱藏型宏單元被配置成一個(gè)輸入，就不會(huì)從矩陣中分配到乘積項(xiàng)輸入。在圖8中，結(jié)構(gòu)位C7可以從輸入/輸出引腳選擇反饋信號(hào)輸入到寄存器，進(jìn)而取代了來(lái)自乘積項(xiàng)矩陣的輸入。對(duì)于每一個(gè)LAB而言，都有一個(gè)異步復(fù)位，置位乘積項(xiàng)。無(wú)論是時(shí)鐘信號(hào)，復(fù)位或置位信號(hào)都有優(yōu)先級(jí)選擇器。對(duì)于CY7C371i/372i 與CY7C373i/374i/375i系列器件，每一個(gè)宏單元分別可以在兩個(gè)時(shí)鐘與四個(gè)時(shí)鐘中進(jìn)行選擇。在一個(gè)LAB中的所有宏單元都接受同一優(yōu)先級(jí)的時(shí)鐘信號(hào)，復(fù)位或置位信號(hào)。優(yōu)先級(jí)可以在每一個(gè)LAB中單獨(dú)配置。圖8描述了輸入/輸出宏單元，輸入/輸出同隱藏型宏單元。圖9與圖10描述了輸入/時(shí)鐘及輸入宏單元。輸入宏單元提供了組合邏輯，門限邏輯，單寄存器，或雙寄存器輸入的靈活性。CY7C371i/372i系列器件有兩個(gè)輸入/時(shí)鐘引腳和四個(gè)輸入引腳。CY7C373i/374i/375i系列器件有四個(gè)輸入/時(shí)鐘引腳和兩個(gè)輸入引腳。為了增加靈活性，每個(gè)時(shí)鐘都可配置成正的或負(fù)的優(yōu)先級(jí)。為了全面了解FLASH370i乘積項(xiàng)分配器的操作過(guò)程，需要介紹乘積項(xiàng)分配器設(shè)計(jì)中的兩個(gè)重要方面：乘積項(xiàng)分配與乘積項(xiàng)共享。分配是指將乘積項(xiàng)資源賦予宏單元。傳統(tǒng)的PLD設(shè)計(jì)沒(méi)有分配的靈活性。每一個(gè)宏單元都有其固定的，特定的乘積項(xiàng)輸入。在許多的設(shè)計(jì)中，每一個(gè)宏單元要求的乘積項(xiàng)輸入往往不同，這也就對(duì)為每個(gè)宏單元指定不同的乘積項(xiàng)提出了要求。乘積項(xiàng)共享指的是一個(gè)乘積項(xiàng)被多個(gè)宏單元所共用。不同宏單元的邏輯等式有時(shí)候包含了一樣的最小項(xiàng)。將生成的這一乘積項(xiàng)由多個(gè)宏單元所共用而不是為每個(gè)宏單元都分別生成這一最小項(xiàng)，可以極大的提高其性能。圖11是FLASH370i系列器件乘積項(xiàng)分配器的概念表示，乘積項(xiàng)分配器的功能如同一個(gè)分塊的或陣列，他為每個(gè)宏單元提供0到16 個(gè)乘積項(xiàng)的相或。每一個(gè)乘積項(xiàng)都可以單獨(dú)被分配與共享。這一結(jié)構(gòu)在將某個(gè)宏單元的乘積項(xiàng)用做另一個(gè)宏單元的輸入上有著一些優(yōu)勢(shì)。圖12是MACH乘積項(xiàng)分配器的概念上的表示。他不能在宏單元之間共享乘積項(xiàng)。四個(gè)乘積項(xiàng)的每一個(gè)都只能布道一個(gè)宏單元。每四個(gè)一組的乘積項(xiàng)分配是粒度更高的布局，但不是也很有效。為了展現(xiàn)這一低效之處。考慮一個(gè)需要五個(gè)乘積項(xiàng)輸入的宏單元。兩個(gè)乘積項(xiàng)簇一共可以提供8個(gè)可能的乘積項(xiàng)輸入。因?yàn)槭Ｓ嗟某朔e項(xiàng)不能夠再布通到其他的宏單元，這樣就浪費(fèi)了來(lái)自另一簇宏單元的3個(gè)乘積項(xiàng)資源。MAX7000型乘積項(xiàng)分配器示意圖表現(xiàn)了擴(kuò)展乘積項(xiàng)的應(yīng)用（圖13）。擴(kuò)展項(xiàng)有兩路通道通過(guò)矩陣，可以產(chǎn)生高效的應(yīng)用。這些擴(kuò)展項(xiàng)由LAB中的所有乘積項(xiàng)所共享。擴(kuò)展項(xiàng)應(yīng)用的不足之處在于兩路通路通過(guò)矩陣時(shí)的延遲增加。這使得時(shí)間模型復(fù)雜化，也使得器件的性能與擴(kuò)展乘積項(xiàng)的應(yīng)用相聯(lián)系。與MACH乘積項(xiàng)分配器相同，MAX7000型分配器也有五個(gè)乘積項(xiàng)簇。因而，當(dāng)有多與一個(gè)簇連到某個(gè)宏單元時(shí)，同樣會(huì)有乘積項(xiàng)浪費(fèi)的問(wèn)題。 FLASH370i乘積項(xiàng)分配器提供了最有效的乘積項(xiàng)分配與共享方案。信號(hào)通過(guò)乘積項(xiàng)分配器的傳輸與每一個(gè)宏單元的乘積項(xiàng)數(shù)目沒(méi)有關(guān)系。PIM與乘積項(xiàng)分配器的靈活性使得無(wú)須改變器件引腳即可完成設(shè)計(jì)的修改。輸入與輸出的開(kāi)關(guān)矩陣沒(méi)有必要，那只會(huì)增加額外的延遲并降低器件的性能。FLASH370i系列器件的定時(shí)模式比其他的CPLD更加簡(jiǎn)單，這有以下兩個(gè)原因。首先，所有進(jìn)入LAB的輸入信號(hào)都需通過(guò)PIM。這包括了所有的輸入與輸出，宏單元輸出的反饋，及特定的輸入。其次，通過(guò)乘積項(xiàng)分配器的延遲時(shí)間與分配給宏單元的乘積項(xiàng)數(shù)目無(wú)關(guān)。因此，沒(méi)有擴(kuò)展延遲，沒(méi)有特定的輸入/輸出引腳延遲，也不會(huì)因使用了多達(dá)16個(gè)乘積項(xiàng)而性能降低，或是也不會(huì)因分配與擴(kuò)展乘積項(xiàng)而有延遲。FLASH370i系列器件提供了可以像PLD一樣的時(shí)間預(yù)測(cè)。FLASH370i系列器件的PIM被設(shè)計(jì)成達(dá)到100%的連通性，但也不會(huì)做的很寬以至影響到性能與尺寸。 The FLASH370i Family Of CPLDs This application note covers the following topics: (1) a general discussion of complex programmable logic devices (CPLDs),(2) an overview of the FLASH370i family of CPLDs.Overview of CPLDsCPLDs extend the concept of the PLD to a higher level of integration to improve system performance,use less board space, improve reliability, and reduce cost. Instead of making the PLD bigger with more input terms and product terms, a CPLDarchitecture is compo_ sed of multiple PLDs or logic blocks (LABs) connected together with a programmable interconnect matrix (PIM). Multiple Logic Array Blocks (LABs) provide comparable speed to a PLD because the basic propagation path is through one LAB and each LABs product term array is comparable to a PLD array. Multiple LABs provide the higher integration. The number of LABs in a CPLD is typically between 2 for the smaller CPLDs and 16 for the larger ones. In addition to LABs interconnected by the PIM, are the input/ output macrocells and the dedicated input macrocells. Figures 1 and 2 show the CPLD generic block diagram and the logic block diagram respectively. The architectural components of the LAB are: (1) the product term array, (2) the product term allocator, and (3) the macrocell. The product term array is the same in the CPLD as in the PLD except that the inputs into the array can now also come from the PIM. The product term allocator is a new concept in the CPLD where product terms are not fixed to a macrocell with its associated input/output pin but can be routed to different macrocells depending on where they are needed. The result is a more efficient allocation of product terms and higher integration. Implementation of the product term allocator varies across CPLD vendors which is more fully discussed in the section describing the features of the FLASH370i family. The macrocell accepts the single output of the product term allocator which is the ORing of a variable number of product terms. In some macrocells this input feeds into a two input XOR gate with the other input potentially carrying the Q feedback.This configures the D flip flop to a T flip flop which can provide an improvement in capacity for certain designs such as counters. After the XOR gate, the macrocell is configurable as registered, combinatorial, and in some cases latched. There are two kinds of macrocells which are input/output dedicated and buried. Dedicated macrocells output to the input/ output macrocell and also provide feedback into the product term array. Buried macrocells only provide feedback into the product term array. The function of the PIM is to distribute the needed fraction of the total available resources, all outputs from the LAB and possibly also dedicated inputs and inputs/outputs, to the appropriate LAB. There are two common methods of PIM implementation: array based interconnect and mux based interconnect. Figure 3 shows the data path of communication between two LABs using the array based interconnect. In the array based interconnect, each output of the LAB can potentially connect to any number of PIM input terms through a memory element.Each PIM input term is assigned to a specific LAB and functions as an input term into the LABs product term array. In this example only four PIM input terms are shown two going to LAB1 and two going to LAB2. There is a sense amp per input term to detect the logic level, buffer the signal, and drive it into the LAB. The true and complement of the PIM signal feed into the product term array (not shown in the figure). Since every LAB output can connect to any PIM input, the interconnect is considered 100 percent routable. It never limits the ability of the device to fit logic. A macrocell output can connect to one or multiple PIM input terms. The major drawback from using a memory element as an interconnect is the slower propagation delay than the muxed based interconnect. Figure 4 shows the data path of communication between two LABs using the muxed based interconnect. In the muxed based interconnect a mux chooses one of a number of potential PIM input terms into the LAB. The PIM input terms differ from the array based interconnect in that they are output from a 1 of n (where “n” is the number of inputs of the mux) mux instead of the output of a wired nor memory array. The inputs into the muxes are all the outputs of the LABs as well as dedicated inputs and input/output pins. Figure 3 shows two PIM input terms output from two 4-to-1 muxes. In this example, macrocell 2 from LAB1 and macrocell 2 from LAB2 both show 2 chances to route into the muxes with other inputs having only 1 chance. The wider the mux (the number of inputs into the mux) the more likely all desired inputs into each LAB will be successfully routed and the more chances each signal gets to route into a LAB. The disadvantage of larger muxes is a larger slower propagation delay through the PIM and increased die size. Implementations of mux-based interconnect vary in the size of the mux.Features of the FLASH370i CPLDsThe FLASH370i family of CPLDs offers densities from 2 to 8 LABs. Figure 5 shows the block diagram of the CY7C374i/5i with 8 LABs. The even numbers of the family (372i,374i) bury half of the macrocells for maximum integration with the same pinout as the (371i,373i,375i) respectively. Table 1 shows the family members offered. Figures 6 and 7 show the product term array, product term allocator, macrocells, and input/output macrocells for the FLASH370i family. Each LAB features 36 inputs, which can adequately handle 32-bit operations plus control signals with one pass through the LAB. The product term array features the true and complement polarities of each PIM output signal for a total of 72 inputs. 80 standard product terms are provided to the product term allocator which allocates from 0 to 16 product terms to each of the 16 macrocells. Additionally, 6 special product terms are also generated in the product term array. They are an asynchronous preset, asynchronous reset, and two groups of 2 bank output enable product terms. The output macrocell (Figure 8) provides a selection of four output controlling options: (1) control from one output enable;(2) control from a second output enable;(3) permanently enabled;(4) permanently disabled. Each LAB contains 4 output enable product terms, 2 for the upper 8 macrocells and 2 for the lower 8 macrocells. The state macrocell (Figure 8) contains options to register, latch, or send data through combinatorially. For the input/output macrocell there is an additional output polarity mux to improve capacity before the signal goes to the input/output macrocell. For buried macrocells there is an additional mux which can configure the state register as an input register. If the buried macrocell is configured as an input, zero product terms will be allocated from the array. In Figure 8 architecture bit C7 can choose the feedback from the input/output pin as the input into the register instead of from the product term array. There is one asynchronous preset and reset product term for each LAB. There are polarity muxes for the clocks, preset and reset. Each macrocell can choose among two clocking options for the CY7C371i/372i and four clocking options for the CY7C373i/374i/375i. All macrocells in a LAB receive the same polarity of the clock, set and reset. Polarities are configurable per LAB. Figure 8 shows the input/output macrocell and input/output plus buried macrocell. Figures 9 and 10 show the input/clock and input macrocells. The input macrocell provides the flexibility to let the input enter combinatorially, latched, single registered, or double registered (for maximum metastability performance). For the CY7C371i/372i there are two input/clocks pins and four input pins. For the CY7C373i/374i/375i there are four input/clock pins and two input pins. For added flexibility, each clock can be configurable for either positive or negative polarity. In order to fully understand the operation of the FLASH370i product term allocator, two important aspects of product term allocator design need to be introduced: product term steering and product term sharing. Steering refers to the assignment of a product term resource to a macrocell. In the traditional PLD there is no steering flexibility. Each macrocell has assigned product terms that can only be used by that macrocell. In many designs each macrocell requires a different number of product terms putting an emphasis on the ability to allocate product terms individually on an as needed basis. Product term sharing refers to a product term being used by multiple macrocells. The logic equations for different macrocells sometimes contain the same minterm. Instead of generating this same minterm multiple times, it is generated on only one product term and shared across macrocells, thereby improving capacity. Figure 11 is a conceptual representation of the FLASH370i product term allocator. The product term allocator functions like a segmented OR array by ORing from 0 to 16 product terms for each macrocell. Product terms can be steered and shared on an individual basis. This architecture has several advantages over other implementa_ tions that steer product terms away from one macrocell to serve another.CPLD can be quickly listed the CPLD structure is coarse-grained structure of the programmable logic device. It is rich in logic resources (ie logic gate with a high proportion of the Register) and the highly flexible routing resources. CPLD is linked to routing, and routing of the FPGA split open. FPGA may be more flexible, but including many of the jumper, the slow pace than CPLD. CPLD to-array (array of clusters) with the form, by the horizontal and vertical channel routing link. These routing channel signal to the pin on the device or Scientology, and to the logic of internal CPLD group linked up. CPLD has called coarse, because, in comparison with the routing number, the logical group to be large. CPLD logic FPGA group than the basic unit of much larger, FPGA is fine. CPLD CPLD function block is the most basic unit of Acer unit. A macro-element contains a register (using as many as 16 items as the product of its input), and other useful properties. Acer because each module of the 16 product items, So designers can deploy a large number of combinational logic without additional trails. This is why the CPLD is considered to be logical rich. Type. Acer unit in the form of logic module with (LB), each logic module from the 16-unit. Implementation of a macro-element AND operation, then an OR operation to achieve the combinational logic. Each group is the logic logic module 8, all groups are logically connected to the Internet with a programmable matrix. Each group also includes two single-port memory logic module and a multi-port memory access module. The former is 8 per module, memory 192b, which included four, 096b memory and dedicated communication can be configured as single-port and multi-port or with dedicated FIFO control logic. CPLD is one of the benefits to the density of the device can provide more I / O number, and sometimes even as much as 70%. CPLD simple sequential model is superior to other programmable structure is that it is simple and predictable time-series model. This simple sequential model must be attributed to the CPLD coarse-grained characteristics. CPLD in a given period of time for wider equal status, and had nothing to do with the routing. This capability is key to the success of the design, not only to accelerate the initial design work, but also to accelerate the design debugging process. Coarse-grained structure of the advantages of CPLD CPLD is coarse-grained structure, which means that the access device through the path less switch, corresponding to the delay also small. Thus, compared to equivalent FPGA, CPLD can work at a higher frequency, with better performance. CPLD Another advantage is that its software compiler fast, because of its easy routing architecture design tasks laid off more easy to implement.Figure 12 is a conceptual representation of the MACH product term allocator. It shows no ability to share product terms across macrocells. Each cluster of four product terms can route to only one macrocell. The product terms are routed in groups of four which is a much higher granularity of product term allocation and not as efficient.To demonstrate this inefficiency, consider a macrocell that needs five product terms to implement its logic. Two product term clusters with a total of eight available product terms are needed. This wastes the resources of three product terms from the borrowed cluster since these product terms can not be rerouted to another macrocell. TheMAX7000 product term allocator representation (Figure 13) shows the use of expander terms. Expander terms allow two passes thro