基于CPLD和單片機(jī)的8位頻率計(jì)

1、 if (digitselected=8 dig7=1; P1=segmeng7digit8; dig8=0; void display(void interrupt 1/中斷處理函數(shù) ET0=0; TR0=0; TH0=T0_High_Init; TL0=T0_Low_Init; TR0=1; if (+counter=9 counter=1; displaydigit(counter; ET0=1; CPLD 程序部分： module frequency(foutp8Hz,dataout,latchout,digisele,clrdata,signalin,clockin input cl

2、ockin; /連接晶振 input signalin; /連接示波器輸入信號(hào) input clrdata; /單片機(jī)的 clrdata input 2:0 digisele; /單片機(jī)的 digisele2、1、0 output latchout; output foutp8hz； /lathout、foutp8hz 實(shí)際上是中間變量 wy1 output 3:0 dataout; /單片機(jī)的 P0 wire latch; wire latchout; reg sigt; reg 3:0 dataout; wire3:0 dig0,dig1,dig2,dig3,dig4,dig5,dig6,

3、dig7; freqdiv divone(foutp8hz,clockin; assign latch=foutp8hz; /取反 wy2 assign latchout=latch;/分頻鏈之后的信號(hào) and andone(sigt,latchout,signalin;/與門 bcdcounter gewei(dig0,clrdata,sig;/BCD 個(gè)位 bcdcounter shiwei(dig1,clrdata,dig03;/BCD 十位 bcdcounter baiwei(dig2,clrdata,dig13;/BCD 百位 bcdcounter qianwei(dig3,clrd

4、ata,dig23;/BCD 千位 bcdcounter wanwei(dig4,clrdata,dig33;/BCD 萬位 bcdcounter shiwanwei(dig5,clrdata,dig43;/BCD 十萬位 bcdcounter baiwanwei(dig6,clrdata,dig53;/BCD 百萬位 bcdcounter qianwanwei(dig7,clrdata,dig63;/BCD 千萬位 always (posedge clockin case (digisele 3b000:dataout = digi0; 3b001:dataout = digi1; 3b01

5、0:dataout = digi2; 3b011:dataout = digi3; 3b100:dataout = digi4; 3b101:dataout = digi5; 3b110:dataout = digi6; 3b111:dataout = digi7; endcase endmodule module freqdiv(foutp8hz,clock;/七次十分頻將 8MHZ 分頻為 0.8HZ input clock; output foutp8hz; wire f800khz,f80khz,f8khz,f800hz,f80hz,f8hz,fp8hz; tenfreqdiv f1(

6、f800khz,clock; tenfreqdiv f2(f80khz,f800khz; tenfreqdiv f3(f8khz,f80khz; tenfreqdiv f4(f800hz,f8khz; tenfreqdiv f5(f80hz,f800hz; tenfreqdiv f6(f8hz,f80hz; tenfreqdiv f7(fp8hz,f8hz; assign foutp8hz=fp8hz; endmodule module tenfreqdiv(f10div,clock;/十分頻 input clock; output f10div; reg 3:0 freqout; always (posedge clock if (freqout=9 freqout=0; else freqout=fout+1; assign f10div=freqout3; endmodule module bcdcounter(bcdout,clr,clock;/BCD 碼計(jì)數(shù) input clock; input clr; output 3:0bcdout; reg 3:0 bcdout; always (nege