4×4矩陣鍵盤控制實驗

1、精選優(yōu)質(zhì)文檔-傾情為你奉上精選優(yōu)質(zhì)文檔-傾情為你奉上專心-專注-專業(yè)專心-專注-專業(yè)精選優(yōu)質(zhì)文檔-傾情為你奉上專心-專注-專業(yè)44矩陣鍵盤控制實驗一、實驗內(nèi)容摘要 設(shè)計一個44鍵盤接口控制器，在QuartusII軟件上實現(xiàn)基設(shè)計，將其與開發(fā)板連接，實現(xiàn)電路功能。當(dāng)按下某一鍵時，4位LED上顯示對應(yīng)的鍵值，以二進制代碼形式從0至F顯示。二、實驗源代碼 LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY DEBOUNCING ISPORT(clk, key:IN STD_LOGIC ;clr

2、: INSTD_LOGIC;dly_out, dif_out: OUTSTD_LOGIC);END DEBOUNCING;ARCHITECTURE a OF DEBOUNCING ISSIGNAL sample,dly,diff: STD_LOGIC;BEGINfree_counter:blocksignal QQ:std_logic_vector(4 downto 0);signal d0:std_logic;beginprocess (CLR,clk)beginif clr=0 thend0=0;QQ0);ELSif clkevent and clk=1 thend0=QQ(4);-QQ的

3、最高位同時作為d0信號,即d0的周期為2的5次方個clk.QQ=QQ+1;end if;end process;sample=not(QQ(4) and (not d0);-當(dāng)d0為0,QQ(4)為1時,sample產(chǎn)生采樣脈沖,低電平時間為1個clkend block free_counter;debunce:blocksignal d0,d1,s,r:std_logic;beginprocess(clk,clr)beginif clr=0 thendly=0;elsif rising_edge(clk) thenif sample=1 thend1=d0;d0=key;s=d0 and d

4、1;r=not d0 and not d1;if s=0 and r=0 thendly=dly;elsif s=0 and r=1 thendly=0;elsif s=1 and r=0 thendly=1;elsedly=0;end if;end if;end if;end process;dly_out=dly;end block debunce;differential:blocksignal d1,d0:std_logic;beginprocess(clk,clr)beginif clr=0 thend0=0;d1=0;elsif rising_edge(clk) thend1=d0

5、;d0=dly;end if;diff=d0 and not d1;end process;dif_out=diff;end block differential;END a;-*-* 4x4標準鍵盤板讀取并點亮實驗箱底板上的L1-L4-* Filename: keyboard4_4-* 掃描鍵盤，譯碼并點亮實驗箱底板上的L1-L4-* 已加入去抖程序-*library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity keyboard4_4 is port( rst : in std_logic;

6、clk_in : in std_logic; keyin : in std_logic_vector(3 downto 0); scan : out std_logic_vector(3 downto 0); leds : out std_logic_vector(3 downto 0);state: out std_logic;M : out std_logic_vector(3 downto 0) );end keyboard4_4;architecture keyboard4_4_arch of keyboard4_4 is-*component debouncingport(key :

7、 IN STD_LOGIC ; clk,clr : IN STD_LOGIC ; dly_out : OUT STD_LOGIC ) ;end component ;-*- signal clkfrq : std_logic; signal cntscn : std_logic_vector(1 downto 0); signal scnlin : std_logic_vector(3 downto 0); signal cntfrq : std_logic_vector(14 downto 0); signal lednum : std_logic_vector(7 downto 0);si

8、gnal key_tmp : std_logic_vector(3 downto 0);signal clk : std_logic;signal cntfrq1 : std_logic_vector(5 downto 0);beginM = 0101;-鍵盤功能選擇 scan = not scnlin; lednum = scnlin & (not key_tmp); -key_tmp keyin(0) ,DLY_OUT = key_tmp(0) ,clr=rst,clk = CLK);U2: debouncing PORT MAP (KEY = keyin(1) ,dly_out = ke

9、y_tmp(1) ,clr=rst,clk = CLK );U3: debouncing PORT MAP (key = keyin(2) ,dly_out = key_tmp(2) ,clr=rst, clk = CLK );U4: debouncing PORT MAP (key = keyin(3) ,dly_out = key_tmp(3) ,clr=rst, clk = CLK );END block debounuing ;-*- process(rst,clk_in) - 晶振為40MHz，進行40000分頻產(chǎn)生去抖時鐘（1000Hz) begin if rst = 0 then

10、 cntfrq 0); elsif rising_edge(clk_in) then if (cntfrq = 1111 or not (key_tmp=1110 or key_tmp=1101 or key_tmp=1011 or key_tmp=0111) ) then -if (cntfrq = 1111 or key_tmp=1111 ) then -if cntfrq = 1111 then cntfrq 0); clk = not clk;-去抖時鐘 else cntfrq = cntfrq + 1; end if; end if; end process; process(rst

11、,clk) -去抖時鐘,50分頻,形成掃描時鐘beginif rst = 0 thenclkfrq = 0;cntfrq1 0);elsif rising_edge(clk) thenif cntfrq1 = 11000 thencntfrq1 0);clkfrq = not clkfrq;elsecntfrq1 = cntfrq1 + 1;end if;end if;end process; process(rst,clkfrq) - 根據(jù)掃描時鐘產(chǎn)生掃描線 begin if rst = 0 then cntscn = 00; elsif rising_edge(clkfrq) then i

12、f cntscn = 11 then cntscn = 00; else cntscn scnlin scnlin scnlin scnlin null; end case; end if; end process; process(rst, clkfrq) - 根據(jù)按鍵點亮相應(yīng)的leds begin if(rst = 0 ) then leds leds leds leds leds leds leds leds leds leds leds leds leds leds leds leds leds null; end case; end if; end process;process(r

13、st,key_tmp)beginif(rst = 0 ) thenstate = 1;elsif (key_tmp=1110 or key_tmp=1101 or key_tmp=1011 or key_tmp=0111) thenstate = 0;elsif (key_tmp=1111) thenstate ;Directory，Name，Top-Level Entity選擇Next;Add Files選擇Next；eq oac(,4)Family&Device Setting中，F(xiàn)amily選擇Cyclone IV，Packge選擇FBGA，Pin Count選擇256，Speed gr

14、ade選擇8，Available device選擇EP3C25F256C8，在點擊Next;eq oac(,5)EDA Tool Settings選擇Next;eq oac(,6)最后在Summary中選擇Finish。6、點擊Assignments,選擇Remove Assignments，全選后取消All和Device Assigments。7、預(yù)編譯，選擇Process/Start/Start Analysis&Synthesis，進行綜合。8、選擇File/New，選擇Design File/VHDL File。9、輸入44矩陣鍵盤控制的消抖代碼。10、點擊Project，選擇Set as Top-Level Entity，設(shè)置成頂層模塊。 11、點擊Assignments,選擇Remove Assignments，全選后取消All和Device Assigments。 12、進行引腳鎖定13、預(yù)編譯，選擇Process/Start/Start Analysis&Synthe