八位數(shù)碼管的動(dòng)態(tài)顯示VHDL程序

1、-entity seg_display isport( clk : in std_logic; -定義動(dòng)態(tài)掃描時(shí)鐘信號(hào)reset : in std_logic; -定義復(fù)位信號(hào)ledag : out std_logic_vector(6 downto 0; -定義數(shù)碼管的七段輸出信號(hào)del : out std_logic_vector(2 downto 0 -定義八位數(shù)碼管位置顯示信號(hào);end seg_display;-architecture whphtao of seg_display issignal clk1Khz : std_logic; -數(shù)碼管掃描時(shí)鐘signal clk1hz

2、: std_logic; -計(jì)數(shù)時(shí)鐘signal cq : std_logic_vector(3 downto 0;-計(jì)數(shù)值beginPROCESS(clk -產(chǎn)生1hz信號(hào)variable cnt : INTEGER RANGE 0 TO 49999999;BEGINIF clk='1' AND clk'event THENIF cnt=49999999 THEN cnt:=0;ELSEIF cnt<25000000 THEN clk1hz<='1'ELSE clk1hz<='0'END IF;cnt:=cnt+1;E

3、ND IF;END IF;end process;PROCESS(clk -產(chǎn)生1Khz信號(hào)variable cnt1 : INTEGER RANGE 0 TO 49999;BEGINIF clk='1' AND clk'event THENIF cnt1=49999 THEN cnt1:=0;ELSEIF cnt1<25000 THEN clk1khz<='1'ELSE clk1khz<='0'END IF;cnt1:=cnt1+1;END IF;end process;process(clk1hz,resetvari

4、able cqi : std_logic_vector(3 downto 0;beginif reset='0' then cqi:=(others =>'0'- 計(jì)數(shù)器異步復(fù)位elsif clk1hz'event and clk1hz='1' then-檢測(cè)時(shí)鐘上升沿if cqi<15 then cqi:=cqi+1;else cqi:=(others =>'0'end if;-end if;end if;cq<=cqi;-計(jì)數(shù)值向端口輸出end process;process(clk1KHZ -

5、數(shù)碼管動(dòng)態(tài)掃描variable dount :std_logic_vector(2 downto 0;beginif clk1kHZ'event and clk1kHZ='1' then-檢測(cè)時(shí)鐘上升沿dount:=dount+1;-計(jì)數(shù)器dount累加end if;del<=dount;end process;process(cq-數(shù)碼管顯示begincase cq iswhen "0000" => ledag <="0111111"when "0001" => ledag <=

6、"0000110"when "0010" => ledag <="1011011"when "0011" => ledag <="1001111"when "0100" => ledag <="1100110"when "0101" => ledag <="1101101"when "0110" => ledag <="1111

7、101"when "0111" => ledag <="0000111"when "1000" => ledag <="1111111"when "1001" => ledag <="1101111"when "1010" => ledag <="1110111"when "1011" => ledag <="1111100"when "1100" => ledag <="0111001"when "1101" => ledag <="1011110"when "1110" => ledag <="1111001&