杭電-計(jì)組實(shí)驗(yàn)5-6-7(章老師不插板實(shí)驗(yàn)報(bào)告)

1、精選優(yōu)質(zhì)文檔-傾情為你奉上實(shí)驗(yàn)報(bào)告 2016年 5 月 10 日 成績(jī)： 姓名學(xué)號(hào)班級(jí)專(zhuān)業(yè)計(jì)算機(jī)科學(xué)與技術(shù)課程名稱計(jì)算機(jī)組成原理課程設(shè)計(jì)任課老師章復(fù)嘉指導(dǎo)老師章復(fù)嘉機(jī)位號(hào)實(shí)驗(yàn)序號(hào)5，6，7實(shí)驗(yàn)名稱寄存器堆設(shè)計(jì)實(shí)驗(yàn)，MIPS匯編器與模擬器實(shí)驗(yàn)取，指令與譯指令實(shí)驗(yàn)時(shí)間第6周第14周實(shí)驗(yàn)地點(diǎn)一教225實(shí)驗(yàn)設(shè)備號(hào)一、實(shí)驗(yàn)程序源代碼實(shí)驗(yàn)五module main(input 0:0 wea,input 7:2 addra,output 31:0 douta,input Clk,Reset,input Write_Reg,input 4:0 W_Addr,input 31:0 W_Data,input 4:

2、0 R_Addr_A,R_Addr_B,output 31:0 R_Data_A,R_Data_B );RAM A1( .clka(Clk), / input clka .wea(wea), / input 0 : 0 wea .addra(addra7:2), / input 5 : 0 addra .dina(R_Data_A), / input 31 : 0 dina .douta(douta) / output 31 : 0 douta);four B1( .Clk(Clk), .Reset(Reset), .Write_Reg(Write_Reg), .W_Addr(W_Addr),

3、 .W_Data(W_Data), .R_Addr_A(R_Addr_A), .R_Addr_B(R_Addr_B), .R_Data_A(R_Data_A), .R_Data_B(R_Data_B) );endmodulemodule RAM(input clka,input 0:0 wea,input 7:2 addra,input 31:0 dina,output 31:0 douta);RAM_B your_instance_name ( .clka(clka), / input clka .wea(wea), / input 0 : 0 wea .addra(addra7:2), /

4、 input 5 : 0 addra .dina(dina), / input 31 : 0 dina .douta(douta) / output 31 : 0 douta);endmodule#100;Reset=0;Clk=0;#100;W_Addr=5'b11011;W_Data=32'b;Clk=0;#50;Clk=1;#100;R_Addr_A=5'b11011;R_Addr_B=0;Clk=0;Write_Reg=0;#100;R_Addr_A=5'b11011;Write_Reg=0;Clk=0;W_Addr=0;W_Data=0;#10;Clk

5、=0;wea=1;addra=8'b;#10;Clk=1;#100;wea=0;addra=8'b;#100;Clk=0;#10;Clk=1;B#100;clka=0;wea=0;addra=6'b;dina=32'b;#100;clka=1;wea=0;addra=6'b;dina=32'b;#100;clka=0;wea=1;addra=6'b;dina=32'b;#100;clka=1;wea=1;addra=6'b;dina=32'b實(shí)驗(yàn)6nor $1,$0,$0; #$1=FFFF_FFFFsltu $2

6、,$0,$1; #$2=0，000_0001add $3,$2,$2; #$3=0000_0002add $4,$3,$2; #$4=0000_0003add $5,$4,$3; #$5=0000_0005add $6,$5,$3; #$6=0000_0007sllv $7,$6,$2; #$7=0000_000Eadd $9,$5,$6; #$9=0000_000Csllv $8,$6,$9; #$8=0000_7000xor $9,$1,$8; #$9=FFFF_8FFFadd $10,$9,$1; #$10=FFFF_8FFEsub $11,$8,$7; #$11=0000_6FF2su

7、b $12,$7,$8; #$12=FFFF_900Eadd $13,$9,$12; #$13=FFFF_200Dor $14,$9,$12; #$14=FFFF_9FFFor $15,$6,$7; #$15=0000_000Fnor $16,$5,$7; #$16=FFFF_FFF0add $17,$7,$3; #$17=0000_0010sllv $18,$8,$17; #$18=7000_0000sllv $19,$3,$17; #$19=0002_0000sllv $20,$19,$7; #$20=8000_0000sub $21,$1,$20; #$21=7FFF_FFFFor $2

8、2,$18,$21; #$22=7FFF_FFFFadd $23,$20,$22; #$23=FFFF_FFFFsub $24,$18,$19; #$24=6FFE_0000sub $25,$19,$18; #$25=9002_0000xor $26,$1,$18; #$26=8FFF_FFFFsltu $27,$22,$20; #$27=0000_0001sltu $28,$26,$20; #$28=0000_0000sub $29,$22,$2; #$29=7FFF_FFFEadd $30,$20,$2; #$30=8000_0001add $31,$11,$26; #$31=9000_6

9、FF1實(shí)驗(yàn)7：module Inst(clk,rst,Inst_Code,PC_new,PC);input wire clk,rst;output wire 31:0 Inst_Code;output wire31:0 PC_new;output reg31:0 PC;initialbeginPC=32'h0000_0000;endROM Inst_ROM( .addra(PC7:2), / input 5 : 0 addra.clka(clk), / input clka .douta(Inst_Code) / output 31 : 0 douta);assign PC_new=P

10、C+4;always( negedge clk or posedge rst)beginif(rst)PC=32'h0000_0000;else PC=24'h,PC_new7:0;endendmoduleInst_ROM文件：memory_initialization_radix=16;memory_initialization_vector=,b,00a33020,00a64820,00e86022,012c6820,012c7025,00c77825,00a78027,00e38820,00f3a004,0034a822,0255b025,0296b820,0253c022,0272c822,0032d026,02d4d82b,0354e02b,02c2e822,0282f020,017af820;二、仿真波形實(shí)驗(yàn)五實(shí)驗(yàn)六實(shí)驗(yàn)七：三、電路圖實(shí)驗(yàn)5實(shí)驗(yàn)7四、引腳配置（約束文件）五、思考與探索實(shí)驗(yàn)5：（3）設(shè)計(jì)實(shí)現(xiàn)