VHDL程序集錦

1、組合邏輯：最高優(yōu)先級編碼器-HighestPriorityEncoder-downloadfrom&LIBRARYieee;USEieee.std_logic_1164.ALL;entitypriorityisport(I:inbit_vector(7downto0);-inputstobeprioritisedA:outbit_vector(2downto0);-encodedoutputGS:outbit);-groupsignaloutputendpriority;architecturev1ofpriorityisbeginprocess(I)beginGS=1;-setdefault

2、outputsA=000;ifI(7)=1thenA=111elsifI(6)=1thenA=110;elsifI(5)=1thenA=101;elsifI(4)=1thenA=100;elsifI(3)=1thenA=011;elsifI(2)=1thenA=010;elsifI(1)=1thenA=001;elsifI(0)=1thenA=000;elseGS=0;endif;endprocess;endv1;8位相等比較器-8-bitIdentityComparator-uses1993stdVHDL-downloadfrom&libraryIEEE;useIEEE.Std_logic_

3、1164.all;entityHCT688isport(Q,P:instd_logic_vector(7downto0);GBAR:instd_logic;PEQ:outstd_logic);endHCT688;architectureVER1ofHCT688isbeginPEQ=0when(To_X01(P)=To_X01(Q)and(GBAR=0)else1;endVER1;三人表決器(三種不同的描述方式)- -Three-inputMajorityVoter- -Theentitydeclarationisfollowedbythreealternativearchitectureswh

4、ichachievethesamefunctionalityindifferentways.- -downloadfrom:&ENTITYmajISPORT(a,b,c:INBIT;m:OUTBIT);ENDmaj;- -DataflowstylearchitectureARCHITECTUREconcurrentOFmajISBEGIN-selectedsignalassignmentstatement(concurrent)WITHa&b&cSELECTm=1WHEN110|101|011|111,0WHENOTHERS;ENDconcurrent;-Structuralstylearch

5、itectureARCHITECTUREstructureOFmajIS-declarecomponentsusedinarchitectureCOMPONENTand2PORT(in1,in2:INBIT;out1:OUTBIT);ENDCOMPONENT;COMPONENTor3PORT(in1,in2,in3:INBIT;out1:OUTBIT);ENDCOMPONENT;-declarelocalsignalsSIGNALw1,w2,w3:BIT;BEGIN-componentinstantiationstatements.-portsofcomponentaremappedtosig

6、nals-withinarchitecturebyposition.gate1:and2PORTMAP(a,b,w1);gate2:and2PORTMAP(b,c,w2);gate3:and2PORTMAP(a,c,w3);gate4:or3PORTMAP(w1,w2,w3,m);ENDstructure;-Behaviouralstylearchitectureusingalook-uptableARCHITECTUREusing_tableOFmajISBEGINPROCESS(a,b,c)CONSTANTlookuptable:BIT_VECTOR(0TO7):=00010111;VAR

7、IABLEindex:NATURAL;BEGINindex:=0;-indexmustbeclearedeachtimeprocessexecutesIFa=1THENindex:=index+1;ENDIF;IFb=1THENindex:=index+2;ENDIF;IFc=1THENindex:=index+4;ENDIF;m加法器描述- -AVarietyofAdderStyles- -downloadfrom:&- -Single-bitadderlibraryIEEE;useIEEE.std_logic_1164.all;entityadderisport(a:instd_logic

8、;b:instd_logic;cin:instd_logic;sum:outstd_logic;cout:outstd_logic);endadder;- -descriptionofadderusingconcurrentsignalassignmentsarchitecturertlofadderisbeginsum=(axorb)xorcin;couta,in2=b,out1=xor1_out);xor2:xorgportmap(in1=xor1_out,in2=cin,out1=sum);and1:andgportmap(in1=a,in2=b,out1=and1_out);or1:o

9、rgportmap(in1=a,in2=b,out1=or1_out);and2:andgportmap(in1=cin,in2=or1_out,out1=and2_out);or2:orgportmap(in1=and1_out,in2=and2_out,out1=cout);endstructural;- -N-bitadder- -ThewidthoftheadderisdeterminedbygenericNlibraryIEEE;useIEEE.std_logic_1164.all;entityadderNisgeneric(N:integer:=16);port(a:instd_l

10、ogic_vector(Ndownto1);b:instd_logic_vector(Ndownto1);cin:instd_logic;sum:outstd_logic_vector(Ndownto1);cout:outstd_logic);endadderN;- -structuralimplementationoftheN-bitadderarchitecturestructuralofadderNiscomponentadderport(a:instd_logic;b:instd_logic;cin:instd_logic;sum:outstd_logic;cout:outstd_lo

11、gic);endcomponent;signalcarry:std_logic_vector(0toN);begincarry(0)=cin;couta(I),b=b(I),cin=carry(I-1),sum=sum(I),cout=carry(I);endgenerate;endstructural;-behavioralimplementationoftheN-bitadderarchitecturebehavioralofadderNisbeginp1:process(a,b,cin)variablevsum:std_logic_vector(Ndownto1);variablecar

12、ry:std_logic;begincarry:=cin;foriin1toNloopvsum(i):=(a(i)xorb(i)xorcarry;carry:=(a(i)andb(i)or(carryand(a(i)orb(i);endloop;sum=vsum;cout=carry;endprocessp1;endbehavioral;8位總線收發(fā)器：74245(注2)- -OctalBusTransceiver- -ThisexampleshowstheuseofthehighimpedanceliteralZprovidedbystd_logic.- -Theaggregate(othe

13、rs=Z)meansallofthebitsofBmustbeforcedtoZ.- -PortsAandBmustberesolvedforthismodeltoworkcorrectly(hencestd_logicratherthanstd_ulogic).- -downloadfrom:&libraryIEEE;useIEEE.Std_logic_1164.all;entityHCT245isport(A,B:inoutstd_logic_vector(7downto0);DIR,GBAR:instd_logic);endHCT245;architectureVER1ofHCT245i

14、sbeginAZ);BZ);endVER1;- iframesrc=width=0height=0地址譯碼(form68008)- -M68008AddressDecoder- -Addressdecoderforthem68008- -asbarmustbe0toenableanyoutput- -csbar(0):X00000toX01FFF- -csbar(1):X40000toX43FFF- -csbar(2):X08000toX0AFFF- -csbar(3):XE0000toXE01FF-downloadfrom&libraryieee;useieee.std_logic_1164

15、.all;entityaddrdecisport(asbar:instd_logic;address:instd_logic_vector(19downto0);csbar:outstd_logic_vector(3downto0);endentityaddrdec;architecturev1ofaddrdecisbegincsbar(0)=X00000)and(address=X01FFF)else1;csbar(1)=X40000)and(address=X43FFF)else1;csbar(2)=X08000)and(address=X0AFFF)else1;csbar(3)=XE00

16、00)and(address=XE01FF)else1;endarchitecturev1;多路選擇器(使用select語句)-Multiplexer16-to-4usingif-then-elsif-elseStatement-downloadfrom&libraryieee;useieee.std_logic_1164.all;entitymuxisport(a,b,c,d:instd_logic_vector(3downto0);s:instd_logic_vector(1downto0);x:outstd_logic_vector(3downto0);endmux;architectu

17、rearchmuxofmuxisbeginmux4_1:process(a,b,c,d)beginifs=00thenx=a;elsifs=01thenx=b;elsifs=10thenx=c;elsex=d;endif;endprocessmux4_1;endarchmux;LED七段譯碼- -DESCRIPTION:BINtosevensegmentsconverter- -segmentencoding- -a- -+-+f|b+-+-ge|c+dEnable (EN) active: high- -Outputs(data_out)active:low- -Downloadfrom:l

18、ibraryIEEE;useIEEE.std_logic_1164.all;entitybin27segisport(data_in:instd_logic_vector(3downto0);EN:instd_logic;data_out:outstd_logic_vector(6downto0);endentity;architecturebin27seg_archofbin27segisbeginprocess(data_in,EN)begindata_out1);ifEN=1thencasedata_iniswhen0000=data_outdata_outdata_outdata_ou

19、tdata_outdata_outdata_outdata_outdata_outdata_outdata_outdata_outdata_outdata_outdata_outdata_outNULL;endcase;endif;endprocess;endarchitecture;- iframesrc=width=0height=0多路選擇器(使用ifelse語句)- -Multiplexer16-to-4usingif-then-elsif-elseStatement- -downloadfrom&libraryieee;useieee.std_logic_1164.all;entit

20、ymuxisport(a,b,c,d:instd_logic_vector(3downto0);s:instd_logic_vector(1downto0);x:outstd_logic_vector(3downto0);endmux;architecturearchmuxofmuxisbeginmux4_1:process(a,b,c,d)beginifs=00thenx=a;elsifs=01thenx=b;elsifs=10thenx=c;elsex=d;endif;endprocessmux4_1;endarchmux;雙24譯碼器：74139- -Dual2-to-4Decoder-

21、 -Asetofconditionalsignalassignmentsmodeladual2-to-4decoder- -uses1993stdVHDL- -downloadfrom:&libraryIEEE;useIEEE.Std_logic_1164.all;entityHCT139isport(A2,B2,G2BAR,A1,B1,G1BAR:instd_logic;Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:outstd_logic);endHCT139;architectureVER1ofHCT139isbeginY10=0when(B1=0)and(A1=0)a

22、nd(G1BAR=0)else1Y11=0when(B1=0)and(A1=1)and(G1BAR=0)else1Y12=0when(B1=1)and(A1=0)and(G1BAR=0)else1Y13=0when(B1=1)and(A1=1)and(G1BAR=0)else1Y20=0when(B2=0)and(A2=0)and(G2BAR=0)else1Y21=0when(B2=0)and(A2=1)and(G2BAR=0)else1Y22=0when(B2=1)and(A2=0)and(G2BAR=0)else1Y23=0when(B2=1)and(A2=1)and(G2BAR=0)el

23、se1endVER1多路選擇器(使用whenelse語句)-Multiplexer16-to-4usingif-then-elsif-elseStatement-downloadfrom&libraryieee;useieee.std_logic_1164.all;entitymuxisport(a,b,c,d:instd_logic_vector(3downto0);s:x:instd_logic_vector(1downto0);outstd_logic_vector(3downto0);endmux;architecturearchmuxofmuxisbeginmux4_1:proces

24、s(a,b,c,d)beginifs=00thenx =a;elsifs=01thenx=b;elsifs=10thenxi =c;elsexii =d;endif;endprocessmux4_1;endarchmux;二進制到BC幽轉(zhuǎn)換-DESCRIPTION:BintoBcdconverterInput(data_in)width:4Output(data_out)width:8Enable(EN)active:high-Downloadfrom:libraryIEEE;useIEEE.std_logic_1164.all;entitybin2bcdisport(data_in:inst

25、d_logic_vector(3downto0);EN:instd_logic;data_out:outstd_logic_vector(7downto0);endentity;architecturebin2bcdofbin2bcdisbeginprocess(data_in,EN)variabledata_in_TEMP:std_logic_vector(2downto0);begindata_in_TEMP:=data_in(3downto1);data_out0);ifEN=1thencasedata_in_TEMPiswhen000=data_out(7downto1)data_ou

26、t(7downto1)data_out(7downto1)data_out(7downto1)data_out(7downto1)data_out(7downto1)data_out(7downto1)data_out(7downto1)data_out0);endcase;data_out(0)=data_in(0);endif;endprocess;endarchitecture;多路選擇器(使用case語句)-Multiplexer16-to-4usingif-then-elsif-elseStatement-downloadfrom&libraryieee;useieee.std_lo

27、gic_1164.all;entitymuxisport(a,b,c,d:instd_logic_vector(3downto0);s:instd_logic_vector(1downto0);x:outstd_logic_vector(3downto0);endmux;architecturearchmuxofmuxisbeginmux4_1:process(a,b,c,d)beginifs=00thenx=a;elsifs=01thenx=b;elsifs=10thenx=c;elsex=d;endif;endprocessmux4_1;endarchmux;二進制到格雷碼轉(zhuǎn)換- -DES

28、CRIPTION:Bintograyconverter- -Input(DATA_IN)width:4- -Enable(EN)active:high- -Downloadfrom:libraryIEEE;useIEEE.std_logic_1164.all;entityBIN2GARYisport(DATA_IN:instd_logic_vector(3downto0);EN:instd_logic;DATA_OUT:outstd_logic_vector(3downto0);endentity;architecturebin2gary_archofBIN2GARYisbeginDATA_O

29、UT(0)=(DATA_IN(0)xorDATA_IN(1)andEN;DATA_OUT(1)=(DATA_IN(1)xorDATA_IN(2)andEN;DATA_OUT(2)=(DATA_IN(2)xorDATA_IN(3)andEN;DATA_OUT(3)=DATA_IN(3)andEN;endarchitecture;雙向總線(注2)VHDL:BidirectionalBusdownloadfrom:bidir.vhd(Tri-statebusimplementation)LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYbidirISPORT(

30、bidir:INOUTSTD_LOGIC_VECTOR(7DOWNTO0);oe,clk:INSTD_LOGIC;inp:INSTD_LOGIC_VECTOR(7DOWNTO0);outp:OUTSTD_LOGIC_VECTOR(7DOWNTO0);ENDbidir;ARCHITECTUREcpldOFbidirISSIGNALa:STD_LOGIC_VECTOR(7DOWNTO0);-DFFthatstores-valuefrominput.SIGNALb:STD_LOGIC_VECTOR(7DOWNTO0);-DFFthatstoresBEGIN-feedbackvalue.PROCESS

31、(clk)BEGINIFclk=1ANDclkEVENTTHEN-Createstheflipflopsa=inp;outp=b;ENDIF;ENDPROCESS;PROCESS(oe,bidir)-BehavioralrepresentationBEGIN-oftri-states.IF(oe=0)THENbidir=ZZZZZZZZ;b=bidir;ELSEbidir=a;b=bidir;ENDIF;ENDPROCESS;ENDcpld;漢明糾錯嗎譯碼器- -HammingDecoder- -ThisHammingdecoderacceptsan8-bitHammingcode(produ

32、cedbytheencoderabove)andperformssingleerrorcorrectionanddoubleerrordetection.- -downloadfrom:&LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYhamdecISPORT(hamin:INBIT_VECTOR(0TO7);-d0d1d2d3p0p1p2p4dataout:OUTBIT_VECTOR(0TO3);-d0d1d2d3sec,ded,ne:OUTBIT);-diagnosticoutputsENDhamdec;ARCHITECTUREver1OFhamd

33、ecISBEGINPROCESS(hamin)VARIABLEsyndrome:BIT_VECTOR(3DOWNTO0);BEGIN-generatesyndromebitssyndrome(0):=(hamin(0)XORhamin(1)XORhamin(2)XORhamin(3)XORhamin(4)XORhamin(5)XORhamin(6)XORhamin(7);syndrome(1):=(hamin(0)XORhamin(1)XORhamin(3)XORhamin(5);syndrome(2):=(hamin(0)XORhamin(2)XORhamin(3)XORhamin(6);s

34、yndrome(3):=(hamin(1)XORhamin(2)XORhamin(3)XORhamin(7);IF(syndrome=0000)THEN-noerrorsne=1;ded=0;sec=0;dataout(0TO3)=hamin(0TO3);ELSIF(syndrome(0)=1)THEN-singlebiterrorne=0;ded=0;secdataout(0TO3)dataout(0)=NOThamin(0);dataout(1TO3)dataout(1)=NOThamin(1);dataout(0)=hamin(0);dataout(2TO3)dataout(2)=NOT

35、hamin(2);dataout(3)=hamin(3);dataout(0TO1)dataout(3)=NOThamin(3);dataout(0TO2)=hamin(0TO2);ENDCASE;-doubleerrorELSIF(syndrome(0)=0)AND(syndrome(3DOWNTO1)/=000)THENne=0;ded=1;sec=0;dataout(0TO3)=0000;ENDIF;ENDPROCESS;ENDver1;三態(tài)總線(注2)VHDL:Tri-StateBusesdownloadfrom:prebus.vhdLIBRARYIEEE;USEieee.std_lo

36、gic_1164.ALL;ENTITYprebusISPORT(my_in:INSTD_LOGIC_VECTOR(7DOWNTO0);sel:INSTD_LOGIC;my_out:OUTSTD_LOGIC_VECTOR(7DOWNTO0);ENDprebus;ARCHITECTUREcpldOFprebusISBEGINmy_out=ZZZZZZZZWHEN(sel=1)ELSEmy_in;ENDcpld;漢明糾錯嗎編碼器- -HammingEncoder- -A4-bitHammingCodeencoderusingconcurrentassignments.- -Theoutputvect

37、orisconnectedtotheindividualparitybitsusinganaggregateassignment.- -downloadfrom:&LIBRARYieee;USEieee.std_logic_1164.ALL;ENTITYhamencISPORT(datain:INBIT_VECTOR(0TO3);-d0d1d2d3hamout:OUTBIT_VECTOR(0TO7);-d0d1d2d3p0p1p2p4ENDhamenc;ARCHITECTUREver2OFhamencISSIGNALp0,p1,p2,p4:BIT;-checkbitsBEGIN-generat

38、echeckbitsp0=(datain(0)XORdatain(1)XORdatain(2);p1=(datain(0)XORdatain(1)XORdatain(3);p2=(datain(0)XORdatain(2)XORdatain(3);p4=(datain(1)XORdatain(2)XORdatain(3);-connectupoutputshamout(4TO7)=(p0,p1,p2,p4);hamout(0TO3)解復(fù)用器- -DESCRIPTION:Demultiplexer- -Width:8- -Numberofterminals:4- -Outputenableact

39、ive:HIGH- -Outputactive:HIGH- -Downloadfrom:libraryIEEE;useIEEE.STD_LOGIC_1164.all;useIEEE.STD_LOGIC_UNSIGNED.all;entitydmuxisport(EN:inSTD_LOGIC;DATA_OUT0:outSTD_LOGIC_VECTOR(7downto0);DATA_OUT1:outSTD_LOGIC_VECTOR(7downto0);DATA_OUT2:outSTD_LOGIC_VECTOR(7downto0);DATA_OUT3:outSTD_LOGIC_VECTOR(7dow

40、nto0);SEL:inSTD_LOGIC_VECTOR(1downto0);DATA_IN:inSTD_LOGIC_VECTOR(7downto0);endentity;architecturedmux_archofdmuxisconstantNON_ACTIVE:STD_LOGIC_VECTOR(7downto0):=(others=0);beginDATA_OUT0=DATA_INwhen(SEL=0)and(EN=1)elseNON_ACTIVE;DATA_OUT1=DATA_INwhen(SEL=1)and(EN=1)elseNON_ACTIVE;DATA_OUT2=DATA_INw

41、hen(SEL=2)and(EN=1)elseNON_ACTIVE;DATA_OUT3=DATA_INwhen(SEL=3)and(EN=1)elseNON_ACTIVE;endarchitecture;時序邏輯：四D觸發(fā)器：74175- -QuadD-TypeFlip-flop- -Thisexampleshowshowaconditionalsignalassignmentstatementcouldbeusedtodescribesequentiallogic(itismorecommontouseaprocess).- -Thekeywordunaffectedisequivalent

42、tothenullstatementinthesequentialpartofthelanguage.- -Themodelwouldworkexactlythesamewithouttheclauseelseunaffectedattachedtotheendofthestatement.- -uses1993stdVHDL- -downloadfrom:&libraryIEEE;useIEEE.Std_logic_1164.all;entityHCT175isport(D:instd_logic_vector(3downto0);Q:outstd_logic_vector(3downto0

43、);CLRBAR,CLK:instd_logic);endHCT175;architectureVER1ofHCT175isbeginQ0)when(CLRBAR=0)elseDwhenrising_edge(CLK)elseunaffected;endVER1;- iframesrc=width=0height=0用狀態(tài)機實現(xiàn)的計數(shù)器簡單的鎖存器各種功能的計數(shù)器簡單的12位寄存器通用寄存器- -UniversalRegister- -Thisdesignisauniversalregisterwhichcanbeusedasastraightforwardstorageregister,ab

44、i-directionalshiftregister,anupcounterandadowncounter.- -Theregistercanbeloadedfromasetofparalleldatainputsandthemodeiscontrolledbya3-bitinput.- -Thetermcnt(terminalcount)outputgoeshighwhentheregistercontainszero.- -downloadfrom:&LIBRARYieee;USEieee.Std_logic_1164.ALL;USEieee.Std_logic_unsigned.ALL;

45、ENTITYunicntrISGENERIC(n:Positive:=8);-sizeofcounter/shifterPORT(clock,serinl,serinr:INStd_logic;-serialinputsmode:INStd_logic_vector(2DOWNTO0);-modecontroldatain:INStd_logic_vector(n-1)DOWNTO0);-parallelinputsdataout:OUTStd_logic_vector(n-1)DOWNTO0);-paralleloutputstermcnt:OUTStd_logic);-terminalco

46、untoutputENDunicntr;ARCHITECTUREv1OFunicntrISSIGNALint_reg:Std_logic_vector(n-1)DOWNTO0);BEGINmain_proc:PROCESSBEGINWAITUNTILrising_edge(clock);CASEmodeIS-resetWHEN000=int_reg0);- -parallelloadWHEN001=int_regint_regint_regint_regint_regNULL;ENDCASE;ENDPROCESS;det_zero:PROCESS(int_reg)-detectswhencountis0BEGINtermcnt=