基于單片機的步進電機電路控制設計英文文獻及翻譯

基于單片機的步進電機電路控制設計英文文獻及翻譯THESTEPPERMOTORCONTROLCIRCUITBEBASEDONSINGLECHIPMICROCOMPUTERTHEAT89C51ISALOWPOWER,HIGHPERFORMANCECMOS8BITMICROCOMPUTERWITH4KBYTESOFFLASHPROGRAMMABLEANDERASABLEREADONLYMEMORYPEROMTHEDEVICEISMANUFACTUREDUSINGATMELSHIGHDENSITYNONVOLATILEMEMORYTECHNOLOGYANDISCOMPATIBLEWITHTHEINDUSTRYSTANDARDMCS51INSTRUCTIONSETANDPINOUTTHEONCHIPFLASHALLOWSTHEPROGRAMMEMORYTOBEREPROGRAMMEDINSYSTEMORBYACONVENTIONALNONVOLATILEMEMORYPROGRAMMERBYCOMBININGAVERSATILE8BITCPUWITHFLASHONAMONOLITHICCHIP,THEATMELAT89C51ISAPOWERFULMICROCOMPUTERWHICHPROVIDESAHIGHLYFLEXIBLEANDCOSTEFFECTIVESOLUTIONTOMANYEMBEDDEDCONTROLAPPLICATIONSFUNCTIONCHARACTERISTICTHEAT89C51PROVIDESTHEFOLLOWINGSTANDARDFEATURES4KBYTESOFFLASH,128BYTESOFRAM,32I/OLINES,TWO16BITTIMER/COUNTERS,AFIVEVECTORTWOLEVELINTERRUPTARCHITECTURE,AFULLDUPLEXSERIALPORT,ONCHIPOSCILLATORANDCLOCKCIRCUITRYINADDITION,THEAT89C51ISDESIGNEDWITHSTATICLOGICFOROPERATIONDOWNTOZEROFREQUENCYANDSUPPORTSTWOSOFTWARESELECTABLEPOWERSAVINGMODESTHEIDLEMODESTOPSTHECPUWHILEALLOWINGTHERAM,TIMER/COUNTERS,SERIALPORTANDINTERRUPTSYSTEMTOCONTINUEFUNCTIONINGTHEPOWERDOWNMODESAVESTHERAMCONTENTSBUTFREEZESTHEOSCILLATORDISABLINGALLOTHERCHIPFUNCTIONSUNTILTHENEXTHARDWARERESETPINDESCRIPTIONVCCSUPPLYVOLTAGEGNDGROUNDPORT0PORT0ISAN8BITOPENDRAINBIDIRECTIONALI/OPORTASANOUTPUTPORT,EACHPINCANSINKEIGHTTTLINPUTSWHEN1SAREWRITTENTOPORT0PINS,THEPINSCANBEUSEDASHIGHIMPEDANCEINPUTSPORT0MAYALSOBECONFIGUREDTOBETHEMULTIPLEXEDLOWORDERADDRESS/DATABUSDURINGACCESSESTOEXTERNALPROGRAMANDDATAMEMORYINTHISMODEP0HASINTERNALPULLUPSPORT0ALSORECEIVESTHECODEBYTESDURINGFLASHPROGRAMMING,ANDOUTPUTSTHECODEBYTESDURINGPROGRAMVERIFICATIONEXTERNALPULLUPSAREREQUIREDDURINGPROGRAMVERIFICATIONPORT1PORT1ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT1OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT1PINSTHEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT1PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEINTERNALPULLUPSPORT1ALSORECEIVESTHELOWORDERADDRESSBYTESDURINGFLASHPROGRAMMINGANDVERIFICATIONPORT2PORT2ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT2OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT2PINSTHEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT2PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENT,BECAUSEOFTHEINTERNALPULLUPSPORT2EMITSTHEHIGHORDERADDRESSBYTEDURINGFETCHESFROMEXTERNALPROGRAMMEMORYANDDURINGACCESSESTOEXTERNALDATAMEMORYTHATUSE16BITADDRESSESINTHISAPPLICATION,ITUSESSTRONGINTERNALPULLUPSWHENEMITTING1SDURINGACCESSESTOEXTERNALDATAMEMORYTHATUSE8BITADDRESSES,PORT2EMITSTHECONTENTSOFTHEP2SPECIALFUNCTIONREGISTERPORT2ALSORECEIVESTHEHIGHORDERADDRESSBITSANDSOMECONTROLSIGNALSDURINGFLASHPROGRAMMINGANDVERIFICATIONPORT3PORT3ISAN8BITBIDIRECTIONALI/OPORTWITHINTERNALPULLUPSTHEPORT3OUTPUTBUFFERSCANSINK/SOURCEFOURTTLINPUTSWHEN1SAREWRITTENTOPORT3PINSTHEYAREPULLEDHIGHBYTHEINTERNALPULLUPSANDCANBEUSEDASINPUTSASINPUTS,PORT3PINSTHATAREEXTERNALLYBEINGPULLEDLOWWILLSOURCECURRENTIILBECAUSEOFTHEPULLUPSPORT3ALSOSERVESTHEFUNCTIONSOFVARIOUSSPECIALFEATURESOFTHEAT89C51ASLISTEDBELOWPORT3ALSORECEIVESSOMECONTROLSIGNALSFORFLASHPROGRAMMINGANDVERIFICATIONRSTRESETINPUTAHIGHONTHISPINFORTWOMACHINECYCLESWHILETHEOSCILLATORISRUNNINGRESETSTHEDEVICEALE/PROGADDRESSLATCHENABLEOUTPUTPULSEFORLATCHINGTHELOWBYTEOFTHEADDRESSDURINGACCESSESTOEXTERNALMEMORYTHISPINISALSOTHEPROGRAMPULSEINPUTPROGDURINGFLASHPROGRAMMINGINNORMALOPERATIONALEISEMITTEDATACONSTANTRATEOF1/6THEOSCILLATORFREQUENCY,ANDMAYBEUSEDFOREXTERNALTIMINGORCLOCKINGPURPOSESNOTE,HOWEVER,THATONEALEPULSEISSKIPPEDDURINGEACHACCESSTOEXTERNALDATAMEMORYIFDESIRED,ALEOPERATIONCANBEDISABLEDBYSETTINGBIT0OFSFRLOCATION8EHWITHTHEBITSET,ALEISACTIVEONLYDURINGAMOVXORMOVCINSTRUCTIONOTHERWISE,THEPINISWEAKLYPULLEDHIGHSETTINGTHEALEDISABLEBITHASNOEFFECTIFTHEMICROCONTROLLERISINEXTERNALEXECUTIONMODEPSENPROGRAMSTOREENABLEISTHEREADSTROBETOEXTERNALPROGRAMMEMORYWHENTHEAT89C51ISEXECUTINGCODEFROMEXTERNALPROGRAMMEMORY,PSENISACTIVATEDTWICEEACHMACHINECYCLE,EXCEPTTHATTWOPSENACTIVATIONSARESKIPPEDDURINGEACHACCESSTOEXTERNALDATAMEMORYEA/VPPEXTERNALACCESSENABLEEAMUSTBESTRAPPEDTOGNDINORDERTOENABLETHEDEVICETOFETCHCODEFROMEXTERNALPROGRAMMEMORYLOCATIONSSTARTINGAT0000HUPTOFFFFHNOTE,HOWEVER,THATIFLOCKBIT1ISPROGRAMMED,EAWILLBEINTERNALLYLATCHEDONRESETEASHOULDBESTRAPPEDTOVCCFORINTERNALPROGRAMEXECUTIONSTHISPINALSORECEIVESTHE12VOLTPROGRAMMINGENABLEVOLTAGEVPPDURINGFLASHPROGRAMMING,FORPARTSTHATREQUIRE12VOLTVPPXTAL1INPUTTOTHEINVERTINGOSCILLATORAMPLIFIERANDINPUTTOTHEINTERNALCLOCKOPERATINGCIRCUITXTAL2OUTPUTFROMTHEINVERTINGOSCILLATORAMPLIFIEROSCILLATORCHARACTERISTICSXTAL1ANDXTAL2ARETHEINPUTANDOUTPUT,RESPECTIVELY,OFANINVERTINGAMPLIFIERWHICHCANBECONFIGUREDFORUSEASANONCHIPOSCILLATOR,ASSHOWNINFIGURE1EITHERAQUARTZCRYSTALORCERAMICRESONATORMAYBEUSEDTODRIVETHEDEVICEFROMANEXTERNALCLOCKSOURCE,XTAL2SHOULDBELEFTUNCONNECTEDWHILEXTAL1ISDRIVENASSHOWNINFIGURE2THEREARENOREQUIREMENTSONTHEDUTYCYCLEOFTHEEXTERNALCLOCKSIGNAL,SINCETHEINPUTTOTHEINTERNALCLOCKINGCIRCUITRYISTHROUGHADIVIDEBYTWOFLIPFLOP,BUTMINIMUMANDMAXIMUMVOLTAGEHIGHANDLOWTIMESPECIFICATIONSMUSTBEOBSERVEDFIGURE1OSCILLATORCONNECTIONSFIGURE2EXTERNALCLOCKDRIVECONFIGURATIONIDLEMODEINIDLEMODE,THECPUPUTSITSELFTOSLEEPWHILEALLTHEONCHIPPERIPHERALSREMAINACTIVETHEMODEISINVOKEDBYSOFTWARETHECONTENTOFTHEONCHIPRAMANDALLTHESPECIALFUNCTIONSREGISTERSREMAINUNCHANGEDDURINGTHISMODETHEIDLEMODECANBETERMINATEDBYANYENABLEDINTERRUPTORBYAHARDWARERESETITSHOULDBENOTEDTHATWHENIDLEISTERMINATEDBYAHARDWARERESET,THEDEVICENORMALLYRESUMESPROGRAMEXECUTION,FROMWHEREITLEFTOFF,UPTOTWOMACHINECYCLESBEFORETHEINTERNALRESETALGORITHMTAKESCONTROLONCHIPHARDWAREINHIBITSACCESSTOINTERNALRAMINTHISEVENT,BUTACCESSTOTHEPORTPINSISNOTINHIBITEDTOELIMINATETHEPOSSIBILITYOFANUNEXPECTEDWRITETOAPORTPINWHENIDLEISTERMINATEDBYRESET,THEINSTRUCTIONFOLLOWINGTHEONETHATINVOKESIDLESHOULDNOTBEONETHATWRITESTOAPORTPINORTOEXTERNALMEMORYPOWERDOWNMODEINTHEPOWERDOWNMODE,THEOSCILLATORISSTOPPED,ANDTHEINSTRUCTIONTHATINVOKESPOWERDOWNISTHELASTINSTRUCTIONEXECUTEDTHEONCHIPRAMANDSPECIALFUNCTIONREGISTERSRETAINTHEIRVALUESUNTILTHEPOWERDOWNMODEISTERMINATEDTHEONLYEXITFROMPOWERDOWNISAHARDWARERESETRESETREDEFINESTHESFRSBUTDOESNOTCHANGETHEONCHIPRAMTHERESETSHOULDNOTBEACTIVATEDBEFOREVCCISRESTOREDTOITSNORMALOPERATINGLEVELANDMUSTBEHELDACTIVELONGENOUGHTOALLOWTHEOSCILLATORTORESTARTANDSTABILIZEPROGRAMMEMORYLOCKBITSONTHECHIPARETHREELOCKBITSWHICHCANBELEFTUNPROGRAMMEDUORCANBEPROGRAMMEDPTOOBTAINTHEADDITIONALFEATURESLISTEDINTHETABLEBELOWWHENLOCKBIT1ISPROGRAMMED,THELOGICLEVELATTHEEAPINISSAMPLEDANDLATCHEDDURINGRESETIFTHEDEVICEISPOWEREDUPWITHOUTARESET,THELATCHINITIALIZESTOARANDOMVALUE,ANDHOLDSTHATVALUEUNTILRESETISACTIVATEDITISNECESSARYTHATTHELATCHEDVALUEOFEABEINAGREEMENTWITHTHECURRENTLOGICLEVELATTHATPININORDERFORTHEDEVICETOFUNCTIONPROPERLYINTRODUCTIONSTEPPERMOTORSAREELECTROMAGNETICINCREMENTALMOTIONDEVICESWHICHCONVERTDIGITALPULSEINPUTSTOANALOGANGLEOUTPUTSTHEIRINHERENTSTEPPINGABILITYALLOWSFORACCURATEPOSITIONCONTROLWITHOUTFEEDBACKTHATIS,THEYCANTRACKANYSTEPPOSITIONINOPENLOOPMODE,CONSEQUENTLYNOFEEDBACKISNEEDEDTOIMPLEMENTPOSITIONCONTROLSTEPPERMOTORSDELIVERHIGHERPEAKTORQUEPERUNITWEIGHTTHANDCMOTORSINADDITION,THEYAREBRUSHLESSMACHINESANDTHEREFOREREQUIRELESSMAINTENANCEALLOFTHESEPROPERTIESHAVEMADESTEPPERMOTORSAVERYATTRACTIVESELECTIONINMANYPOSITIONANDSPEEDCONTROLSYSTEMS,SUCHASINCOMPUTERHARDDISKDRIVERSANDPRINTERS,XYTABLES,ROBOTMANIPULATORS,ETCALTHOUGHSTEPPERMOTORSHAVEMANYSALIENTPROPERTIES,THEYSUFFERFROMANOSCILLATIONORUNSTABLEPHENOMENONTHISPHENOMENONSEVERELYRESTRICTSTHEIROPENLOOPDYNAMICPERFORMANCEANDAPPLICABLEAREAWHEREHIGHSPEEDOPERATIONISNEEDEDTHEOSCILLATIONUSUALLYOCCURSATSTEPPINGRATESLOWERTHAN1000PULSE/S,ANDHASBEENRECOGNIZEDASAMIDFREQUENCYINSTABILITYORLOCALINSTABILITY1,ORADYNAMICINSTABILITY2INADDITION,THEREISANOTHERKINDOFUNSTABLEPHENOMENONINSTEPPERMOTORS,THATIS,THEMOTORSUSUALLYLOSESYNCHRONISMATHIGHERSTEPPINGRATES,EVENTHOUGHLOADTORQUEISLESSTHANTHEIRPULLOUTTORQUETHISPHENOMENONISIDENTIFIEDASHIGHFREQUENCYINSTABILITYINTHISPAPER,BECAUSEITAPPEARSATMUCHHIGHERFREQUENCIESTHANTHEFREQUENCIESATWHICHTHEMIDFREQUENCYOSCILLATIONOCCURSTHEHIGHFREQUENCYINSTABILITYHASNOTBEENRECOGNIZEDASWIDELYASMIDFREQUENCYINSTABILITY,ANDTHEREISNOTYETAMETHODTOEVALUATEITMIDFREQUENCYOSCILLATIONHASBEENRECOGNIZEDWIDELYFORAVERYLONGTIME,HOWEVER,ACOMPLETEUNDERSTANDINGOFITHASNOTBEENWELLESTABLISHEDTHISCANBEATTRIBUTEDTOTHENONLINEARITYTHATDOMINATESTHEOSCILLATIONPHENOMENONANDISQUITEDIFFICULTTODEALWITH384LCAOANDHMSCHWARTZMOSTRESEARCHERSHAVEANALYZEDITBASEDONALINEARIZEDMODEL1ALTHOUGHINMANYCASES,THISKINDOFTREATMENTSISVALIDORUSEFUL,ATREATMENTBASEDONNONLINEARTHEORYISNEEDEDINORDERTOGIVEABETTERDESCRIPTIONONTHISCOMPLEXPHENOMENONFOREXAMPLE,BASEDONALINEARIZEDMODELONECANONLYSEETHATTHEMOTORSTURNTOBELOCALLYUNSTABLEATSOMESUPPLYFREQUENCIES,WHICHDOESNOTGIVEMUCHINSIGHTINTOTHEOBSERVEDOSCILLATORYPHENOMENONINFACT,THEOSCILLATIONCANNOTBEASSESSEDUNLESSONEUSESNONLINEARTHEORYTHEREFORE,ITISSIGNIFICANTTOUSEDEVELOPEDMATHEMATICALTHEORYONNONLINEARDYNAMICSTOHANDLETHEOSCILLATIONORINSTABILITYITISWORTHNOTINGTHATTAFTANDGAUTHIER3,ANDTAFTANDHARNED4USEDMATHEMATICALCONCEPTSSUCHASLIMITCYCLESANDSEPARATRICESINTHEANALYSISOFOSCILLATORYANDUNSTABLEPHENOMENA,ANDOBTAINEDSOMEVERYINSTRUCTIVEINSIGHTSINTOTHESOCALLEDLOSSOFSYNCHRONOUSPHENOMENONNEVERTHELESS,THEREISSTILLALACKOFACOMPREHENSIVEMATHEMATICALANALYSISINTHISKINDOFSTUDIESINTHISPAPERANOVELMATHEMATICALANALYSISISDEVELOPEDTOANALYZETHEOSCILLATIONSANDINSTABILITYINSTEPPERMOTORSTHEFIRSTPARTOFTHISPAPERDISCUSSESTHESTABILITYANALYSISOFSTEPPERMOTORSITISSHOWNTHATTHEMIDFREQUENCYOSCILLATIONCANBECHARACTERIZEDASABIFURCATIONPHENOMENONHOPFBIFURCATIONOFNONLINEARSYSTEMSONEOFCONTRIBUTIONSOFTHISPAPERISTORELATETHEMIDFREQUENCYOSCILLATIONTOHOPFBIFURCATION,THEREBY,THEEXISTENCEOFTHEOSCILLATIONISPROVEDTHEORETICALLYBYHOPFTHEORYHIGHFREQUENCYINSTABILITYISALSODISCUSSEDINDETAIL,ANDANOVELQUANTITYISINTRODUCEDTOEVALUATEHIGHFREQUENCYSTABILITYTHISQUANTITYISVERYEASYTOCALCULATE,ANDCANBEUSEDASACRITERIATOPREDICTTHEONSETOFTHEHIGHFREQUENCYINSTABILITYEXPERIMENTALRESULTSONAREALMOTORSHOWTHEEFFICIENCYOFTHISANALYTICALTOOLTHESECONDPARTOFTHISPAPERDISCUSSESSTABILIZINGCONTROLOFSTEPPERMOTORSTHROUGHFEEDBACKSEVERALAUTHORSHAVESHOWNTHATBYMODULATINGTHESUPPLYFREQUENCY5,THEMIDFREQUENCYINSTABILITYCANBEIMPROVEDINPARTICULAR,PICKUPANDRUSSELL6,7HAVEPRESENTEDADETAILEDANALYSISONTHEFREQUENCYMODULATIONMETHODINTHEIRANALYSIS,JACOBISERIESWASUSEDTOSOLVEAORDINARYDIFFERENTIALEQUATION,ANDASETOFNONLINEARALGEBRAICEQUATIONSHADTOBESOLVEDNUMERICALLYINADDITION,THEIRANALYSISISUNDERTAKENFORATWOPHASEMOTOR,ANDTHEREFORE,THEIRCONCLUSIONSCANNOTAPPLIEDDIRECTLYTOOURSITUATION,WHEREATHREEPHASEMOTORWILLBECONSIDEREDHERE,WEGIVEAMOREELEGANTANALYSISFORSTABILIZINGSTEPPERMOTORS,WHERENOCOMPLEXMATHEMATICALMANIPULATIONISNEEDEDINTHISANALYSIS,ADQMODELOFSTEPPERMOTORSISUSEDBECAUSETWOPHASEMOTORSANDTHREEPHASEMOTORSHAVETHESAMEQDMODELANDTHEREFORE,THEANALYSISISVALIDFORBOTHTWOPHASEANDTHREEPHASEMOTORSUPTODATE,ITISONLYRECOGNIZEDTHATTHEMODULATIONMETHODISNEEDEDTOSUPPRESSTHEMIDFREQUENCYOSCILLATIONINTHISPAPER,ITISSHOWNTHATTHISMETHODISNOTONLYVALIDTOIMPROVEMIDFREQUENCYSTABILITY,BUTALSOEFFECTIVETOIMPROVEHIGHFREQUENCYSTABILITY2DYNAMICMODELOFSTEPPERMOTORSTHESTEPPERMOTORCONSIDEREDINTHISPAPERCONSISTSOFASALIENTSTATORWITHTWOPHASEORTHREEPHASEWINDINGS,ANDAPERMANENTMAGNETROTORASIMPLIFIEDSCHEMATICOFATHREEPHASEMOTORWITHONEPOLEPAIRISSHOWNINFIGURE1THESTEPPERMOTORISUSUALLYFEDBYAVOLTAGESOURCEINVERTER,WHICHISCONTROLLEDBYASEQUENCEOFPULSESANDPRODUCESSQUAREWAVEVOLTAGESTHISMOTOROPERATESESSENTIALLYONTHESAMEPRINCIPLEASTHATOFSYNCHRONOUSMOTORSONEOFMAJOROPERATINGMANNERFORSTEPPERMOTORSISTHATSUPPLYINGVOLTAGEISKEPTCONSTANTANDFREQUENCYOFPULSESISCHANGEDATAVERYWIDERANGEUNDERTHISOPERATINGCONDITION,OSCILLATIONANDINSTABILITYPROBLEMSUSUALLYARISEFIGURE1SCHEMATICMODELOFATHREEPHASESTEPPERMOTORAMATHEMATICALMODELFORATHREEPHASESTEPPERMOTORISESTABLISHEDUSINGQDFRAMEREFERENCETRANSFORMATIONTHEVOLTAGEEQUATIONSFORTHREEPHASEWINDINGSAREGIVENBYVARIALDIA/DTMDIB/DTMDIC/DTDPMA/DT,VBRIBLDIB/DTMDIA/DTMDIC/DTDPMB/DT,VCRICLDIC/DTMDIA/DTMDIB/DTDPMC/DT,WHERERANDLARETHERESISTANCEANDINDUCTANCEOFTHEPHASEWINDINGS,ANDMISTHEMUTUALINDUCTANCEBETWEENTHEPHASEWINDINGS_PMA,_PMBAND_PMCARETHEFLUXLINKAGESOFTHEPHASESDUETOTHEPERMANENTMAGNET,ANDCANBEASSUMEDTOBESINUSOIDFUNCTIONSOFROTORPOSITION_ASFOLLOWPMA1SINN,PMB1SINN2/3,PMC1SINN2/3,WHERENISNUMBEROFROTORTEETHTHENONLINEARITYEMPHASIZEDINTHISPAPERISREPRESENTEDBYTHEABOVEEQUATIONS,THATIS,THEFLUXLINKAGESARENONLINEARFUNCTIONSOFTHEROTORPOSITIONBYUSINGTHEQDTRANSFORMATION,THEFRAMEOFREFERENCEISCHANGEDFROMTHEFIXEDPHASEAXESTOTHEAXESMOVINGWITHTHEROTORREFERTOFIGURE2TRANSFORMATIONMATRIXFROMTHEABCFRAMETOTHEQDFRAMEISGIVENBY8FOREXAMPLE,VOLTAGESINTHEQDREFERENCEAREGIVENBYINTHEABCREFERENCE,ONLYTWOVARIABLESAREINDEPENDENTIACIBCICD0THEREFORE,THEABOVETRANSFORMATIONFROMTHREEVARIABLESTOTWOVARIABLESISALLOWABLEAPPLYINGTHEABOVETRANSFORMATIONTOTHEVOLTAGEEQUATIONS1,THETRANSFERREDVOLTAGEEQUATIONINTHEQDFRAMECANBEOBTAINEDASVQRIQL1DIQ/DTNL1IDN1,VDRIDL1DID/DTNL1IQ,5FIGURE2A,B,CANDD,QREFERENCEFRAMEWHEREL1DLCM,ANDISTHESPEEDOFTHEROTORITCANBESHOWNTHATTHEMOTORSTORQUEHASTHEFOLLOWINGFORM2T3/2N1IQTHEEQUATIONOFMOTIONOFTHEROTORISWRITTENASJD/DT3/2N1IQBFTL,WHEREBFISTHECOEFFICIENTOFVISCOUSFRICTION,ANDTLREPRESENTSLOADTORQUE,WHICHISASSUMEDTOBEACONSTANTINTHISPAPERINORDERTOCONSTITUTETHECOMPLETESTATEEQUATIONOFTHEMOTOR,WENEEDANOTHERSTATEVARIABLETHATREPRESENTSTHEPOSITIONOFTHEROTORFORTHISPURPOSETHESOCALLEDLOADANGLE_8ISUSUALLYUSED,WHICHSATISFIESTHEFOLLOWINGEQUATIOND/DT0,WHERE0ISSTEADYSTATESPEEDOFTHEMOTOREQUATIONS5,7,AND8CONSTITUTETHESTATESPACEMODELOFTHEMOTOR,FORWHICHTHEINPUTVARIABLESARETHEVOLTAGESVQANDVDASMENTIONEDBEFORE,STEPPERMOTORSAREFEDBYANINVERTER,WHOSEOUTPUTVOLTAGESARENOTSINUSOIDALBUTINSTEADARESQUAREWAVESHOWEVER,BECAUSETHENONSINUSOIDALVOLTAGESDONOTCHANGETHEOSCILLATIONFEATUREANDINSTABILITYVERYMUCHIFCOMPAREDTOTHESINUSOIDALCASEASWILLBESHOWNINSECTION3,THEOSCILLATIONISDUETOTHENONLINEARITYOFTHEMOTOR,FORTHEPURPOSESOFTHISPAPERWECANASSUMETHESUPPLYVOLTAGESARESINUSOIDALUNDERTHISASSUMPTION,WECANGETVQANDVDASFOLLOWSVQVMCOSN,VDVMSINN,WHEREVMISTHEMAXIMUMOFTHESINEWAVEWITHTHEABOVEEQUATION,WEHAVECHANGEDTHEINPUTVOLTAGESFROMAFUNCTIONOFTIMETOAFUNCTIONOFSTATE,ANDINTHISWAYWECANREPRESENTTHEDYNAMICSOFTHEMOTORBYAAUTONOMOUSSYSTEM,ASSHOWNBELOWTHISWILLSIMPLIFYTHEMATHEMATICALANALYSISFROMEQUATIONS5,7,AND8,THESTATESPACEMODELOFTHEMOTORCANBEWRITTENINAMATRIXFORMASFOLLOWSFX,UAXFNXBU,10WHEREXDTIQID_UT,UDT1TLUTISDEFINEDASTHEINPUT,AND1DN0ISTHESUPPLYFREQUENCYTHEINPUTMATRIXBISDEFINEDBYTHEMATRIXAISTHELINEARPARTOFF_/,ANDISGIVENBYFNX/REPRESENTSTHENONLINEARPARTOFF_/,ANDISGIVENBYTHEINPUTTERMUISINDEPENDENTOFTIME,ANDTHEREFOREEQUATION10ISAUTONOMOUSTHEREARETHREEPARAMETERSINFXU/,THEYARETHESUPPLYFREQUENCY1,THESUPPLYVOLTAGEMAGNITUDEVMANDTHELOADTORQUETLTHESEPARAMETERSGOVERNTHEBEHAVIOUROFTHESTEPPERMOTORINPRACTICE,STEPPERMOTORSAREUSUALLYDRIVENINSUCHAWAYTHATTHESUPPLYFREQUENCY1ISCHANGEDBYTHECOMMANDPULSETOCONTROLTHEMOTORSSPEED,WHILETHESUPPLYVOLTAGEISKEPTCONSTANTTHEREFORE,WESHALLINVESTIGATETHEEFFECTOFPARAMETER13BIFURCATIONANDMIDFREQUENCYOSCILLATIONBYSETTINGD0,THEEQUILIBRIAOFEQUATION10AREGIVENASANDISITSPHASEANGLEDEFINEDBYARCTAN1L1/R16EQUATIONS12AND13INDICATETHATMULTIPLEEQUILIBRIAEXIST,WHICHMEANSTHATTHESEEQUILIBRIACANNEVERBEGLOBALLYSTABLEONECANSEETHATTHEREARETWOGROUPSOFEQUILIBRIAASSHOWNINEQUATIONS12AND13THEFIRSTGROUPREPRESENTEDBYEQUATION12CORRESPONDSTOTHEREALOPERATINGCONDITIONSOFTHEMOTORTHESECONDGROUPREPRESENTEDBYEQUATION13ISALWAYSUNSTABLEANDDOESNOTRELATETOTHEREALOPERATINGCONDITIONSINTHEFOLLOWING,WEWILLCONCENTRATEONTHEEQUILIBRIAREPRESENTEDBYEQUATION12基于單片機的步進電機電路控制設計89C51是一種帶4K字節(jié)閃爍可編程可擦除只讀存儲器（FPEROMFALSHPROGRAMMABLEANDERASABLEREADONLYMEMORY）的低電壓、高性能CMOS8位微處理器，俗稱單片機。該器件采用ATMEL高密度非易失存儲器制造技術制造，與工業(yè)標準的MCS51指令集和輸出管腳相兼容。由于將多功能8位CPU和閃爍存儲器組合在單個芯片中，ATMEL的89C51是一種高效微控制器，89C2051是它的一種精簡版本。89C單片機為很多嵌入式控制系統(tǒng)提供了一種靈活性高且價廉的方案。功能特點與MCS51兼容4K字節(jié)可編程閃爍存儲器壽命1000寫/擦循環(huán)數據保留時間10年全靜態(tài)工作0HZ24MHZ三級程序存儲器鎖定1288位內部RAM32可編程I/O線兩個16位定時器/計數器5個中斷源可編程串行通道低功耗的閑置和掉電模式片內振蕩器和時鐘電路管腳說明VCC供電電壓。GND接地。P0口P0口為一個8位漏級開路雙向I/O口，每腳可吸收8TTL門電流。當P1口的管腳第一次寫1時，被定義為高阻輸入。P0能夠用于外部程序數據存儲器，它可以被定義為數據/地址的低八位。在FIASH編程時，P0口作為原碼輸入口，當FIASH進行校驗時，P0輸出原碼，此時P0外部必須被拉高。P1口P1口是一個內部提供上拉電阻的8位雙向I/O口，P1口緩沖器能接收輸出4TTL門電流。P1口管腳寫入1后，被內部上拉為高，可用作輸入，P1口被外部下拉為低電平時，將輸出電流，這是由于內部上拉的緣故。在FLASH編程和校驗時，P1口作為第八位地址接收。P2口P2口為一個內部上拉電阻的8位雙向I/O口，P2口緩沖器可接收，輸出4個TTL門電流，當P2口被寫1時，其管腳被內部上拉電阻拉高，且作為輸入。并因此作為輸入時，P2口的管腳被外部拉低，將輸出電流。這是由于內部上拉的緣故。P2口當用于外部程序存儲器或16位地址外部數據存儲器進行存取時，P2口輸出地址的高八位。在給出地址1時，它利用內部上拉優(yōu)勢，當對外部八位地址數據存儲器進行讀寫時，P2口輸出其特殊功能寄存器的內容。P2口在FLASH編程和校驗時接收高八位地址信號和控制信號。P3口P3口管腳是8個帶內部上拉電阻的雙向I/O口，可接收輸出4個TTL門電流。當P3口寫入1后，它們被內部上拉為高電平，并用作輸入。作為輸入，由于外部下拉為低電平，P3口將輸出電流（ILL）這是由于上拉的緣故。P3口也可作為AT89C51的一些特殊功能口口管腳備選功能P30RXD（串行輸入口）P31TXD（串行輸出口）P32/INT0（外部中斷0）P33/INT1（外部中斷1）P34T0（記時器0外部輸入）P35T1（記時器1外部輸入）P36/WR（外部數據存儲器寫選通）P37/RD（外部數據存儲器讀選通）P3口同時為閃爍編程和編程校驗接收一些控制信號。RST復位輸入。當振蕩器復位器件時，要保持RST腳兩個機器周期的高電平時間。ALE/PROG當訪問外部存儲器時，地址鎖存允許的輸出電平用于鎖存地址的地位字節(jié)。在FLASH編程期間，此引腳用于輸入編程脈沖。在平時，ALE端以不變的頻率周期輸出正脈沖信號，此頻率為振蕩器頻率的1/6。因此它可用作對外部輸出的脈沖或用于定時目的。然而要注意的是每當用作外部數據存儲器時，將跳過一個ALE脈沖。如想禁止ALE的輸出可在SFR8EH地址上置0。此時，ALE只有在執(zhí)行MOVX，MOVC指令是ALE才起作用。另外，該引腳被略微拉高。如果微處理器在外部執(zhí)行狀態(tài)ALE禁止，置位無效。/PSEN外部程序存儲器的選通信號。在由外部程序存儲器取指期間，每個機器周期兩次/PSEN有效。但在訪問外部數據存儲器時，這兩次有效的/PSEN信號將不出現。/EA/VPP當/EA保持低電平時，則在此期間外部程序存儲器（0000HFFFFH），不管是否有內部程序存儲器。注意加密方式1時，/EA將內部鎖定為RESET；當/EA端保持高電平時，此間內部程序存儲器。在FLASH編程期間，此引腳也用于施加12V編程電源（VPP）。XTAL1反向振蕩放大器的輸入及內部時鐘工作電路的輸入。XTAL2來自反向振蕩器的輸出。振蕩器特性XTAL1和XTAL2分別為反向放大器的輸入和輸出。該反向放大器可以配置為片內振蕩器。石晶振蕩和陶瓷振蕩均可采用。如采用外部時鐘源驅動器件，XTAL2應不接。由于輸入至內部時鐘信號要通過一個二分頻觸發(fā)器，因此對外部時鐘信號的脈寬無任何要求，但必須保證脈沖的高低電平要求的寬度。FIGURE1OSCILLATORCONNECTIONSFIGURE2EXTERNALCLOCKDRIVE芯片擦除整個PEROM陣列和三個鎖定位的電擦除可通過正確的控制信號組合，并保持ALE管腳處于低電平10MS來完成。在芯片擦操作中，代碼陣列全被寫1且在任何非空存儲字節(jié)被重復編程以前，該操作必須被執(zhí)行。此外，AT89C51設有穩(wěn)態(tài)邏輯，可以在低到零頻率的條件下靜態(tài)邏輯，支持兩種軟件可選的掉電模式。在閑置模式下，CPU停止工作。但RAM，定時器，計數器，串口和中斷系統(tǒng)仍在工作。在掉電模式下，保存RAM的內容并且凍結振蕩器，禁止所用其他芯片功能，直到下一個硬件復位為止。空閑模式在空閑模式下,中央處理器把自己睡所有的微外設保持活躍。該模式調用的軟件。片上的內容的公綿羊、所有的特殊功能寄存器不變在這個模式下?？臻e模式可以終止任何使中斷或由硬件復位。應該指出的是,閑時終止一個硬件復位,設備通常程序執(zhí)行,從簡歷在它停止兩封,機器周期之前,內部重置算法以控制。樣品的硬件抑制進入內部RAM在這種情況下,但進入港口大頭針空洞。消除這種可能性一個出乎意料的寫信給一個港口銷閑時被終止,由復位、指導證明那個中調用一個空閑不應該寫端口銷或外部存儲器。POWERDOWN模式在POWERDOWN模式下,振子是結束了,但這個指令用它召喚“POWERDOWN是最后的指令執(zhí)行。這片上的公綿羊、特殊功能寄存器值,直到POWERDOWN保留自己的方式終止。唯一的退出,是一家五金POWERDOWN重置。SFRS重置重新定義,但不改變樣品的公羊。重置不應該被激活之前VCC回到正常操作水平,都必須保持活躍的時間還不夠久,允許振